Intel 80960HD - Manual (Page 65)

80960HA/HD/HT
Datasheet 65
Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus
ADS
SUP, CT3:0,
W/R
BLAST
DT/R
DEN
A3:2
WAIT
D31:0,
CLKIN
A 2 1 D 1 D 1 D 1 D 1 A
Valid
A3:2 = 00, 01, 10 or 11
D7:0
Byte 0
D7:0
Byte 1
D7:0
Byte 2
D7:0
Byte 3
D/C, LOCK,
A31:4
BE1/A1,
A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 =11 BE0/A0
DP3:0
PCHK
Burst
Bus
Width
Odd Parity
N
XDA
N
WDD
N
WAD
N RDD
29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0
Enabled
1
OFF
0
1
0001
8-Bit X
x
Enabled
1
X
xx
X
xxxxx
1
01
Disabled
0
2
00010
Function
Bit
Value
External
Ready
Control
Pipe-
Lining Parity Enable
N
RAD
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
00
PMCON