Intel 80960HD - Manual (Page 69)

80960HA/HD/HT
Datasheet 69
Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
W/R
A3:2
D31:0,
WAIT
BLAST
DT/R
DEN
CLKIN
IN
D
IN
D
IN
D
IN
D
IN
D’
A 2 1 D 1 D 1 D 1 A’ 2 1
Valid
D
D’
Valid
In-
valid
In-
valid
00 01 10 11 Valid
In-
valid
DP3:0
PCHK
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
2 1
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
Burst
Bus
Width
Odd Parity
N
XDA
N
WDD
N
WAD
N
RDD
29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0
Enabled
1
ON
1
X
xxxx
32-Bit X
x
Enabled
1
X
xx
X
xxxxx
1
01
X
x
2
00010
Function
Bit
Value
External
Ready
Control
Pipe-
Lining Parity Enable
N
RAD
10
PMCON