Intel 80960HD - Manual (Page 93)

80960HA/HD/HT
Datasheet 93
attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”;
attribute Boundary_Length of Ha_Processor: entity is 112;
attribute Boundary_Register of Ha_Processor: entity is
“0 (CBSC_1, DP(3), bidir, X, 17, 1, Z),” &
“1 (CBSC_1, DP(2), bidir, X, 17, 1, Z),” &
“2 (CBSC_1, DP(0), bidir, X, 17, 1, Z),” &
“3 (CBSC_1, DP(1), bidir, X, 17, 1, Z),” &
“4 (BC_4, STEST, input, X),” &
“5 (BC_1, FAILBAR, output3, X, 6, 1, Z),” &
“6 (BC_1, *, control, 1),” &
“7 (BC_4, ONCEBAR, input, X),” &
“8 (BC_4, BOFFBAR, input, X),” &
“9 (CBSC_1, D(0), bidir, X, 17, 1, Z),” &
“10 (CBSC_1, D(1), bidir, X, 17, 1, Z),” &
“11 (CBSC_1, D(2), bidir, X, 17, 1, Z),” &
“12 (CBSC_1, D(3), bidir, X, 17, 1, Z),” &
“13 (CBSC_1, D(4), bidir, X, 17, 1, Z),” &
“14 (CBSC_1, D(5), bidir, X, 17, 1, Z),” &
“15 (CBSC_1, D(6), bidir, X, 17, 1, Z),” &
“16 (CBSC_1, D(7), bidir, X, 17, 1, Z),” &
“17 (BC_1, *, control, 1),” &
“18 (CBSC_1, D(8), bidir, X, 17, 1, Z),” &
“19 (CBSC_1, D(9), bidir, X, 17, 1, Z),” &
“20 (CBSC_1, D(10), bidir, X, 17, 1, Z),” &
“21 (CBSC_1, D(11), bidir, X, 17, 1, Z),” &
“22 (CBSC_1, D(12), bidir, X, 17, 1, Z),” &
“23 (CBSC_1, D(13), bidir, X, 17, 1, Z),” &
“24 (CBSC_1, D(14), bidir, X, 17, 1, Z),” &
“25 (CBSC_1, D(15), bidir, X, 17, 1, Z),” &
“26 (CBSC_1, D(16), bidir, X, 17, 1, Z),” &
“27 (CBSC_1, D(17), bidir, X, 17, 1, Z),” &
“28 (CBSC_1, D(18), bidir, X, 17, 1, Z),” &
“29 (CBSC_1, D(19), bidir, X, 17, 1, Z),” &
“30 (CBSC_1, D(20), bidir, X, 17, 1, Z),” &
“31 (CBSC_1, D(21), bidir, X, 17, 1, Z),” &
“32 (CBSC_1, D(22), bidir, X, 17, 1, Z),” &
“33 (CBSC_1, D(23), bidir, X, 17, 1, Z),” &
“34 (CBSC_1, D(24), bidir, X, 17, 1, Z),” &
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 6 of 8)