Intel 80960HD - Manual (Page 67)

80960HA/HD/HT
Datasheet 67
Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus
ADS
A31:4, SUP,
CT3:0, D/C,
W/R
BLAST
DT/R
DEN
A3:2
WAIT
D31:0,
CLKIN
BE3:0
A 1 A’
D 1 D ’
IN
D’
Valid Valid Invalid
IN
D
LOCK
Valid Valid Invalid
DP3:0
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
PCHK
2 1
Burst
Bus
Width
Odd Parity
N
XDA
N
WDD
N
WAD
N
RDD
29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0
Disabled
0
ON
1
X
xxxx
32-Bit X
x
Enabled
1
X
xx
X
xxxxx
X
xx
X
x
1
00001
Function
Bit
Value
External
Ready
Control
Pipe-
Lining Parity Enable
N
RAD
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
10
Invalid
PMCON