Intel 80960HD - Manual (Page 79)

80960HA/HD/HT
Datasheet 79
Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)
0 4 8 12 16 20 24
0 1 2 3 4 5 6
Triple-Word
Load/Store
Quad-Word
Load/Store
Word, Word,
Word Requests
Requests
4 Word
Requests
Byte Offset
Word Offset
One Three-Word
Request (Aligned)
Trey, Byte, Trey, Byte,
Trey, Byte Requests
Short, Short, Short Requests
Short, Short, Short, Short
Byte, Trey, Byte, Trey, Byte, Trey Requests
Word, Word,
Word Requests
One Four-Word
Request (Aligned)
Trey, Byte, Trey, Byte, Trey, Byte
Trey, Byte Requests
8 Short Requests
Byte, Trey, Byte, Trey,
Byte, Trey, Byte, Trey, Requests
Requests
Word,
Word
Word,
4 Word
NOTES:
1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.