Intel 80960HD User Manual
Page 71
Advertising
80960HA/HD/HT
Datasheet
71
Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus
ADS
A31:4, SUP,
CT3:0, D/C,
BE0/BLC,
W/R
A3:2
BE1/A1
WAIT
BLAST
DT/R
DEN
CLKIN
D15:0
A1=0
D15:0
A1=1
D15:0
A1=0
D15:0
A1=1
D15:0
D’
A
2
1
D
1
D
1
D
1
A’
2
1
Valid
D
D’
Valid
In-
valid
In-
valid
A3:2 = 00 or 10
A3:2 = 01 or 11
Valid
In-
valid
Valid
In-
valid
BE3/BHE,
D31:0,
LOCK
DP3:0
PCHK
2
1
Burst
Bus
Width
Odd
Parity
N
XDA
N
WDD
N
WAD
N
RDD
29
28
21
24
23-22
20
12-8
19-16
15-14
7-6
4-0
Enabled
1
ON
1
X
xxxx
16-Bit
X
x
Enabled
1
X
xx
X
xxxxx
1
01
X
x
2
00010
Function
Bit
Value
External
Ready
Control
Pipe-
Lining
Parity
Enable
N
RAD
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
01
PMCON
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
Advertising