Intel 80960HD - Manual (Page 57)

80960HA/HD/HT
Datasheet 57
Figure 32. Non-Burst, Non-Pipelined Requests without Wait States
In
ADS
A31:2, SUP,
D/C,
LOCK, CT3:0
W/R
BLAST
DT/R
DEN
WAIT
D31:0,
CLKIN
A D A D A D
In
Valid Valid Valid
Burst
Bus
Width
Odd Parity
N
XDA
N
WDD
N
WAD
N
RDD
29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0
Disabled
0
OFF
0
0
0000
X
xx
X
x
Enabled
1
0
00
0
00000
0
00
Disabled
0
0
00000
Out
Function
Bit
Value
BE3:0,
DP3:0
PCHK
External
Ready
Control
Pipe-
Lining Parity Enable
N
RAD
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
PMCON