Other timing requirements – National Instruments DAQ M Series User Manual
Page 40
Chapter 4
Analog Input
4-16
ni.com
Note Refer to the NI 6236 Specifications for the minimum allowable pulse width and the
propagation delay of PFI <0..5>.
Routing AI Sample Clock Signal to an Output
Terminal
You can route ai/SampleClock out to any output PFI <6..9> or RTSI <0..7>
terminal. This pulse is always active high.
You can specify the output to have one of two behaviors. With the pulse
behavior, your DAQ device briefly pulses the PFI terminal once for every
occurrence of ai/SampleClock.
With level behavior, your DAQ device drives the PFI terminal high during
the entire sample.
PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed
outputs.
Other Timing Requirements
Your DAQ device only acquires data during an acquisition. The device
ignores ai/SampleClock when a measurement acquisition is not in progress.
During a measurement acquisition, you can cause your DAQ device to
ignore ai/SampleClock using the ai/PauseTrigger signal.
A counter on your device internally generates ai/SampleClock unless you
select some external source. ai/StartTrigger starts this counter and either
software or hardware can stop it once a finite acquisition completes. When
using an internally generated ai/SampleClock, you also can specify a
configurable delay from ai/StartTrigger to the first ai/SampleClock pulse.
By default, this delay is set to two ticks of the ai/SampleClockTimebase
signal. When using an externally generated ai/SampleClock, you must
ensure the clock signal is consistent with respect to the timing requirements
of ai/ConvertClock. Failure to do so may result in ai/SampleClock pulses
that are masked off and acquisitions with erratic sampling intervals. Refer
to the
section for more information about the
timing requirements between ai/ConvertClock and ai/SampleClock.