Using a delay from sample clock to convert clock, Figure 4-12. ai/sampleclock and ai/convertclock, Other timing requirements – National Instruments DAQ M Series User Manual
Page 43
Chapter 4
Analog Input
© National Instruments Corporation
4-19
PFI <0..5> terminals are fixed inputs. PFI <6..9> terminals are fixed
outputs.
Using a Delay from Sample Clock to Convert Clock
When using an internally generated ai/ConvertClock, you also can specify
a configurable delay from ai/SampleClock to the first ai/ConvertClock
pulse within the sample. By default, this delay is three ticks of
ai/ConvertClockTimebase.
Figure 4-12 shows the relationship of ai/SampleClock to ai/ConvertClock.
Figure 4-12. ai/SampleClock and ai/ConvertClock
Other Timing Requirements
The sample and conversion level timing of M Series devices work such that
clock signals are gated off unless the proper timing requirements are met.
For example, the device ignores both ai/SampleClock and ai/ConvertClock
until it receives a valid ai/StartTrigger signal. After the device recognizes
an ai/SampleClock pulse, it ignores subsequent ai/SampleClock pulses
until it receives the correct number of ai/ConvertClock pulses.
Similarly, the device ignores all ai/ConvertClock pulses until it recognizes
an ai/SampleClock pulse. After the device receives the correct number of
ai/ConvertClock pulses, it ignores subsequent ai/ConvertClock pulses until
it receives another ai/SampleClock. Figure 4-13 shows timing sequences
for a four-channel acquisition (using AI channels 0, 1, 2, and 3) and
demonstrates proper and improper sequencing of ai/SampleClock and
ai/ConvertClock.
ai/ConvertClockTimebase
ai/SampleClock
ai/ConvertClock
Delay
From
Sample
Clock
Convert
Period