National Instruments VXI-MIO Series - Manual (Page 31)

Chapter 3 Hardware Overview
VXI-MIO Series User Manual 3-2  National Instruments Corporation
Figure 3-1. VXI-MIO Series Block Diagram
EEPROM
Config EPROM
VXI
Transceivers
P1 MANTIS P2 MANTIS
VXI Trigger and Clock Circuitry
N.V. RAM
Analog Bus I/O Connector
VXI Bus
3
2
A/D
Converter
+ Programmable Gain Amplifier –
Bank Select
Mux Mode Selection Switches
Ref Buffer
Cal/Aux
Trigger Level
DACS External Trigger
Analog Trigger Circuit
Voltage
REF
Analog Muxes Banks
0-3
Calibration
DACs
Calibration
DACS
Signal
Conditioning
Control Circuitry
DAC FIFOS
DAC0 DAC1
DAQ - STC Analog Input Timing/Control Analog Output Timing/Control
Digital I/O
Trigger Counter/ Timing I/O
RTSI Bus Interface
DMA/
Interrupt Request
Bus
Interface
ACH 48:63 ACH 32:47 ACH 16:31 ACH 0:15
Analog Input Control
EEPROM Control EPF8282
DAQ-STC Interface
DMA
Interface
Bus
Interface
Analog
Output Control
Configuration
EPROM Interface
MITE
VXI Port
MXI Port
I/O Port
ADC FIFO
Timing
VXI Local Bus
VXI Local Bus
Digital I/O (8)
Configuration
Memory
DRAM Circuitry
AD Control
IO Data Lines
AI Control
IO Data Lines
IO Control, IRQ, and DMA Lines
IO Control IO Control IO Control
Address Data Control Signals
Arbitration Signals Interrupts Utility Signals VXI Triggers ECL Triggers CLK10 +/-
CLK10
ECL Triggers (TTL Level)
MODIO Lines
IO Data Lines IO Data Lines
IO Data Lines
IO Data Lines
IO Address Lines IO Address Lines IO Address Lines
Optional
RITSI Bus DRAM Control Signals
RITSI Bus
Logical Address Switch
AD Control