Document Outline

• Lab-PC+
  • Limited Warranty
  • Copyright
  • Trademarks
  • Medical Warning
• Contents
• About This Manual
  • Organization of the Lab-PC+ User Manual
  • Conventions Used in This Manual
  • National Instruments Documentation
  • Customer Communication
• Chapter 1 Introduction
  • About the Lab-PC+
  • What You Need to Get Started
  • Software Programming Choices
    • LabVIEW and LabWindows/CVI Application Software
    • NI-DAQ Driver Software
    • Register-Level Programming
  • Optional Equipment
  • Unpacking
• Chapter 2 Configuration and Installation
  • Board Configuration
    • PC Bus Interface
    • Base I/O Address Selection
    • DMA Channel Selection
    • Interrupt Selection
  • Analog I/O Configuration
    • Analog Output Configuration
      • Bipolar Output Selection
      • Unipolar Output Selection
    • Analog Input Configuration
      • Input Mode
      • DIFF Input (Four Channels
      • RSE Input (Eight Channels, Factory Setting)
      • NRSE Input (Eight Channels)
    • Analog Input Polarity Configuration
      • Bipolar Input Selection
      • Unipolar Input Selection
  • Hardware Installation
• Chapter 3 Signal Connections
  • I/O Connector Pin Description
    • Signal Connection Descriptions
    • Analog Input Signal Connections
  • Types of Signal Sources
    • Floating Signal Sources
    • Ground-Referenced Signal Sources
  • Input Configurations
    • Differential Connection Considerations (DIFF Configuration)
    • Differential Connections for Grounded Signal Sources
    • Differential Connections for Floating Signal Sources
    • Single-Ended Connection Considerations
    • Single-Ended Connections for Floating Signal Sources (RSE Configuration)
    • Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)
    • Common-Mode Signal Rejection Considerations
    • Analog Output Signal Connections
    • Digital I/O Signal Connections
      • Port C Pin Connections
      • Timing Specifications
      • Mode 1 Input Timing
      • Mode 1 Output Timing
      • Mode 2 Bidirectional Timing
    • Timing Connections
      • Data Acquisition Timing Connections
      • General-Purpose Timing Signal Connections and General-Purpose Counter/Timing Signals
  • Cabling
• Chapter 4 Theory of Operation
  • Functional Overview
  • PC I/O Channel Interface Circuitry
  • Analog Input and Data Acquisition Circuitry
    • Analog Input Circuitry
    • Data Acquisition Timing Circuitry
      • Single-Channel Data Acquisition
      • Multiple-Channel (Scanned) Data Acquisition
      • Data Acquisition Rates
  • Analog Output Circuitry
  • Digital I/O Circuitry
  • Timing I/O Circuitry
• Chapter 5 Calibration
  • Calibration Equipment Requirements
  • Calibration Trimpots
  • Analog Input Calibration
    • Board Configuration
    • Bipolar Input Calibration Procedure
    • Unipolar Input Calibration Procedure
  • Analog Output Calibration
  • Board Configuration
  • Bipolar Output Calibration Procedure
  • Unipolar Output Calibration Procedure
    • Adjust the Analog Output Gain
• Appendix A Specifications
  • Analog Input
    • Input Characteristics
    • Transfer Characteristics
    • Amplifier Characteristics
    • Dynamic Characteristics
    • Stability
    • Explanation of Analog Input Specifications
  • Analog Output
    • Output Characteristics
    • Transfer Characteristics
    • Voltage Output
    • Dynamic Characteristics
    • Stability
    • Explanation of Analog Output Specifications
  • Digital I/O
  • Timing I/O
  • Triggers
    • Digital Trigger
  • Bus Interface
  • Power Requirements (from PC)
  • Physical
  • Environment
• Appendix B OKI 82C53 Data Sheet
• Appendix C OKI 82C55A Data Sheet
• Appendix D Register Map and Descriptions
  • Register Map
    • Register Sizes
  • Register Description
    • Register Description Format
    • Configuration and Status Register Group
      • Command Register 1
      • Status Register
      • Command Register 2
      • Command Register 3
      • Command Register 4
      • Analog Input Register Group
      • A/D FIFO Register
      • A/D Clear Register
      • Start Convert Register
      • DMATC Interrupt Clear Register
      • Analog Output Register Group
      • DAC0 Low-Byte (DAC0L), DAC0 High-Byte (DAC0H), DAC1 Low-Byte (DAC1L), and DAC1 High-Byte (DAC1H) Registers
      • 8253 Counter/Timer Register Groups A and B
      • Counter A0 Data Register
      • Counter A1 Data Register
      • Counter A2 Data Register
      • Counter A Mode Register
      • Timer Interrupt Clear Register
      • Counter B0 Data Register
      • Counter B1 Data Register
      • Counter B2 Data Register
      • Counter B Mode Register
      • 8255A Digital I/O Register Group
      • Port A Register
      • Port B Register
      • Port C Register
      • Digital Control Register
      • Interval Counter Register Group
      • Interval Counter Data Register
      • Interval Counter Strobe Register
• Appendix E Register-Level Programming
  • Register Programming Considerations
  • Initializing the Lab-PC+ Board
  • Programming the Analog Input Circuitry
    • Analog Input Circuitry Programming Sequence
    • A/D FIFO Output Binary Modes
    • Clearing the Analog Input Circuitry
  • Programming Multiple A/D Conversions on a Single Input Channel
    • Programming in Controlled Acquisition Mode
    • Programming in Freerun Acquisition Mode
  • External Timing Considerations for Multiple A/D Conversions
    • Using the EXTTRIG Signal to Initiate a Multiple A/D Conversion Data Acquisition Operation (Posttrigger Mode)
    • Using the EXTTRIG Signal to Terminate a Multiple A/D Conversion Data Acquisition Operation (Pretrigger Mode)
    • Using the EXTCONV* Signal to Initiate A/D Conversions
  • Programming Multiple A/D Conversions Using External Timing
    • Programming in Controlled Acquisition Mode
      • Posttrigger Mode
      • Pretrigger Mode
    • Programming in Freerun Acquisition Mode
      • Posttrigger Mode
      • Pretrigger Mode
  • Programming Multiple A/D Conversions with Channel Scanning
  • Programming Multiple A/D Conversions with Interval Scanning
  • Programming Multiple A/D Conversions in Single-Channel Interval Acquisition Mode
  • A/D Interrupt Programming
  • Programming DMA Operation
  • Programming the Analog Output Circuitry
  • Interrupt Programming for the Analog Output Circuitry
  • Programming the Digital I/O Circuitry
    • Register Descriptions and Programming Examples
  • Modes of Operation for the 8255A
    • Mode 0
      • Control Words
      • Programming Examples
    • Mode 1
      • Input
      • Programming Example
      • Output
      • Programming Example
    • Mode 2
      • Control Words
      • Programming Example
      • Single Bit Set/Reset Control Words
      • Single Bit Set/Reset Feature
  • Interrupt Programming for the Digital I/O Circuitry
• Appendix F Customer Communication
• Index
• Glossary
• Figures
  • Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware
  • Figure 2-1. Parts Locator Diagram
  • Figure 2-2. Example Base I/O Address Switch Settings
  • Figure 2-3. DMA Jumper Settings for DMA Channel 3 (Factory Setting)
  • Figure 2-4. DMA Jumper Settings for Disabling DMA Transfers
  • Figure 2-5. Interrupt Jumper Setting IRQ5 (Factory Setting)
  • Figure 2-6. Interrupt Jumper Setting for Disabling Interrupts
  • Figure 2-7. Bipolar Output Jumper Configuration (Factory Setting)
  • Figure 2-8. Unipolar Output Jumper Configuration
  • Figure 2-9. DIFF Input Configuration
  • Figure 2-10. RSE Input Configuration
  • Figure 2-11. NRSE Input Configuration
  • Figure 2-12. Bipolar Input Jumper Configuration (Factory Setting)
  • Figure 2-13. Unipolar Input Jumper Configuration
  • Figure 3-1. Lab-PC+ I/O Connector Pin Assignments
  • Figure 3-2. Lab-PC+ Instrumentation Amplifier
  • Figure 3-3. Differential Input Connections for Grounded Signal Sources
  • Figure 3-4. Differential Input Connections for Floating Sources
  • Figure 3-5. Single-Ended Input Connections for Floating Signal Sources
  • Figure 3-6. Single-Ended Input Connections for Grounded Signal Sources
  • Figure 3-7. Analog Output Signal Connections
  • Figure 3-8. Digital I/O Connections
  • Figure 3-9. EXTCONV* Signal Timing
  • Figure 3-10. Posttrigger Data Acquisition Timing Case 1
  • Figure 3-11. Posttrigger Data Acquisition Timing Case 2
  • Figure 3-12. Pretrigger Data Acquisition Timing
  • Figure 3-13. EXTUPDATE* Signal Timing for Updating DAC Output
  • Figure 3-14. EXTUPDATE* Signal Timing for Generating Interrupts
  • Figure 3-15. Event-Counting Application with External Switch Gating
  • Figure 3-16. Frequency Measurement Application
  • Figure 3-17. General-Purpose Timing Signals
  • Figure 4-1. Lab-PC+ Block Diagram
  • Figure 4-2. PC I/O Interface Circuitry Block Diagram
  • Figure 4-3. Analog Input and Data Acquisition Circuitry Block Diagram
  • Figure 4-4. Analog Output Circuitry Block Diagram
  • Figure 4-5. Digital I/O Circuitry Block Diagram
  • Figure 4-6. Timing I/O Circuitry Block Diagram
  • Figure 4-7. Two-Channel Interval-Scanning Timing
  • Figure 4-8. Single-Channel Interval Timing
  • Figure 4-9. Counter Block Diagram
  • Figure 5-1. Calibration Trimpot Location Diagram
  • Figure E-1. Control-Word Format with Control-Word Flag Set to 1
  • Figure E-2. Control-Word Format with Control-Word Flag Set to 0
• Tables
  • Table 2-1. PC Bus Interface Factory Settings
  • Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space
  • Table 2-3. DMA Channels for the Lab-PC+
  • Table 2-4. Analog I/O Jumper Settings
  • Table 2-5. Input Configurations Available for the Lab-PC+
  • Table 3-1. Recommended Input Configurations for Ground-Referenced and Floating Signal Sources
  • Table 3-2. Port C Signal Assignments
  • Table 4-1. Analog Input Settling Time Versus Gain
  • Table 4-2. Lab-PC+ Maximum Recommended Data Acquisition Rates
  • Table 4-3. Bipolar Analog Input Signal Range Versus Gain
  • Table 4-4. Unipolar Analog Input Signal Range Versus Gain
  • Table 5-1. Voltage Values of ADC Input
  • Table D-1. Lab-PC+ Register Map
  • Table E-1. Unipolar Input Mode A/D Conversion Values (Straight Binary Coding)
  • Table E-2. Bipolar Input Mode A/D Conversion Values (Two’s Complement Coding)
  • Table E-3. Analog Output Voltage Versus Digital Code (Unipolar Mode, Straight Binary Coding)
  • Table E-4. Analog Output Voltage Versus Digital Code (Bipolar Mode, Two’s Complement Coding)
  • Table E-5. ModeÊ0 I/O Configurations
  • Table E-6. Port C Set/Reset Control Words