Document Outline

• PCI-6023E/6024E/6025E User Manual
  • Support
    • Internet
    • Bulletin Board
    • Fax-on-Demand
    • Telephone (USA)
    • International Offices
    • Corporate Headquarters
  • Important Information
  • Contents
  • About This Manual
    • Organization of This Manual
    • Conventions Used in This Manual
    • National Instruments Documentation
    • Related Documentation
    • Customer Communication
  • Chapter 1 Introduction
    • Features of the PCI-6023E, PCI-6024E, and PCI-6025E
    • What You Need to Get Started
    • Unpacking
    • Software Programming Choices
      • National Instruments Application Software
      • NIDAQ Driver Software
      • RegisterLevel Programming
    • Optional Equipment
  • Chapter 2 Installation and Configuration
    • Software Installation
    • Hardware Configuration
    • Hardware Installation
  • Chapter 3 Hardware Overview
    • Analog Input
      • Input Mode
      • Input Range
      • Dither
      • Multichannel Scanning Considerations
    • Analog Output
      • Analog Output Glitch
    • Digital I/O
    • Timing Signal Routing
      • Programmable Function Inputs
      • Board and RTSI Clocks
      • RTSI Triggers
  • Chapter 4 Signal Connections
    • I/O Connector
    • Analog Input Signal Overview
      • Types of Signal Sources
        • Floating Signal Sources
        • GroundReferenced Signal Sources
      • Analog Input Modes
    • Analog Input Signal Connections
      • Differential Connection Considerations (DIFF Input Configuration)
        • Differential Connections for GroundReferenced Signal Sources
        • Differential Connections for Nonreferenced or Floating Signal Sources
      • SingleEnded Connection Considerations
        • SingleEnded Connections for Floating Signal Sources (RSEConfiguration)
        • SingleEnded Connections for Grounded Signal Sources (NRSEConfiguration)
      • CommonMode Signal Rejection Considerations
    • Analog Output Signal Connections
    • Digital I/O Signal Connections
      • All Boards
      • PCI-6025E Only
    • Port C Pin Assignments
    • Digital I/O Power-up State
      • Changing DIO Power-up State to Pulled Low
    • Timing Specifications
      • Mode 1 Input Timing
      • Mode 1 Output Timing
      • Mode 2 Bidirectional Timing
    • Power Connections
    • Timing Connections
      • Programmable Function Input Connections
      • DAQ Timing Connections
        • SCANCLK Signal
        • EXTSTROBE* Signal
        • TRIG1 Signal
        • TRIG2 Signal
        • STARTSCAN Signal
        • CONVERT* Signal
        • AIGATE Signal
        • SISOURCE Signal
      • Waveform Generation Timing Connections
        • WFTRIG Signal
        • UPDATE* Signal
        • UISOURCE Signal
      • GeneralPurpose Timing Signal Connections
        • GPCTR0_SOURCE Signal
        • GPCTR0_GATE Signal
        • GPCTR0_OUT Signal
        • GPCTR0_UP_DOWN Signal
        • GPCTR1_SOURCE Signal
        • GPCTR1_GATE Signal
        • GPCTR1_OUT Signal
        • GPCTR1_UP_DOWN Signal
        • FREQ_OUT Signal
    • Field Wiring Considerations
  • Chapter 5 Calibration
    • Loading Calibration Constants
    • SelfCalibration
    • External Calibration
    • Other Considerations
  • Appendix A Specifications
  • Appendix B Custom Cabling and Optional Connectors
  • Appendix C Common Questions
  • Appendix D Customer Communication
  • Glossary
  • Index
  • Figures
    • Figure 1-1. The Relationship between the Programming Environment, NI DAQ, and Your Hardware
    • Figure 3-1. PCI 6023E, PCI-6024E, and PCI-6025E Block Diagram
    • Figure 3-2. Dither
    • Figure 3-3. CONVERT* Signal Routing
    • Figure 3-4. RTSI Bus Signal Connection
    • Figure 4-1. I/O Connector Pin Assignment for the PCI 6023E/PCI-6024E
    • Figure 4-2. I/O Connector Pin Assignment for the PCI-6025E
    • Figure 4-3. Programmable Gain Instrumentation Amplifier (PGIA)
    • Figure 4-4. Summary of Analog Input Connections
    • Figure 4-5. Differential Input Connections for Ground Referenced Signals
    • Figure 4-6. Differential Input Connections for Nonreferenced Signals
    • Figure 4-7. Single Ended Input Connections for Nonreferenced or Floating Signals
    • Figure 4-8. Single Ended Input Connections for Ground Referenced Signals
    • Figure 4-9. Analog Output Connections
    • Figure 4-10. Digital I/O Connections
    • Figure 4-11. Digital I/O Connections Block Diagram
    • Figure 4-12. DIO Channel Configured for High DIO Power-up State with External Load
    • Figure 4-13. Timing Specifications for Mode 1 Input Transfer
    • Figure 4-14. Timing Specifications for Mode 1 Output Transfer
    • Figure 4-15. Timing Specifications for Mode 2 Bidirectional Transfer
    • Figure 4-16. Timing I/O Connections
    • Figure 4-17. Typical Posttriggered Acquisition
    • Figure 4-18. Typical Pretriggered Acquisition
    • Figure 4-19. SCANCLK Signal Timing
    • Figure 4-20. EXTSTROBE* Signal Timing
    • Figure 4-21. TRIG1 Input Signal Timing
    • Figure 4-22. TRIG1 Output Signal Timing
    • Figure 4-23. TRIG2 Input Signal Timing
    • Figure 4-24. TRIG2 Output Signal Timing
    • Figure 4-25. STARTSCAN Input Signal Timing
    • Figure 4-26. STARTSCAN Output Signal Timing
    • Figure 4-27. CONVERT* Input Signal Timing
    • Figure 4-28. CONVERT* Output Signal Timing
    • Figure 4-29. SISOURCE Signal Timing
    • Figure 4-30. WFTRIG Input Signal Timing
    • Figure 4-31. WFTRIG Output Signal Timing
    • Figure 4-32. UPDATE* Input Signal Timing
    • Figure 4-33. UPDATE* Output Signal Timing
    • Figure 4-34. UISOURCE Signal Timing
    • Figure 4-35. GPCTR0_SOURCE Signal Timing
    • Figure 4-36. GPCTR0_GATE Signal Timing in Edge Detection Mode
    • Figure 4-37. GPCTR0_OUT Signal Timing
    • Figure 4-38. GPCTR1_SOURCE Signal Timing
    • Figure 4-39. GPCTR1_GATE Signal Timing in Edge Detection Mode
    • Figure 4-40. GPCTR1_OUT Signal Timing
    • Figure 4-41. GPCTR Timing Summary
    • Figure B-1. 68 Pin E Series Connector Pin Assignments
    • Figure B-2. 68 Pin Extended Digital Input Connector Pin Assignments
    • Figure B-3. 50 Pin E Series Connector Pin Assignments
    • Figure B-4. 50-Pin Extended Digital Input Connector Pin Assignments
  • Tables
    • Table 3-1. Available Input Configurations
    • Table 3-2. Measurement Precision
    • Table 4-1. I/O Connector Signal Descriptions
    • Table 4-2. I/O Signal Summary
    • Table 4-3. Port C Signal Assignments
    • Table 4-4. Signal Names Used in Timing Diagrams