Analog and timing circuitry, Analog input channels, Analog and timing circuitry -8 – National Instruments SCXI-1121 User Manual
Page 70: Analog input channels -8
Chapter 3
Theory of Operation
3-8
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3.
The serial data is available on MOSI and SPICLK clocks it into the
register.
4.
SS* goes high and D*/A goes high, indicating an end of
communication. This action latches the Configuration Register bits.
When the SCXIbus is reset, all bits in the Configuration Register are
cleared.
The Module ID Register connects to MISO on the SCXIbus. The Module
ID Register is an 8-bit parallel/serial-in serial-out shift register and an SPI
communication adapter. The contents of the Module ID Register are written
onto MISO during the first four bytes of transfer after SS* has been asserted
low. Zeros are written to MISO thereafter until SS* is released and
reasserted. The SCXI-1121 module ID is hex 00000002.
Analog and Timing Circuitry
The SCXIbus provides analog power (±18.5 VDC) that is regulated on the
SCXI-1121 to ±15 VDC, a guard, an analog bus (AB0±), and a chassis
ground (CHSGND). AB0± buses the SCXI-1121 output to other modules
or receives outputs from other modules via the SCXIbus. Refer to the
section later in this chapter for more information. The guard
guards the analog bus, and can be connected via jumper W33 to the analog
ground reference or can be left floating (a connection can be made by
another board).
The data acquisition board analog input and timing is the interface between
the SCXI-1121 output and the data acquisition board. This is fully
described in the following section.
Analog Input Channels
Figure 3-5 is a diagram of the analog input block.