Texas Instruments TMS320C674X - Manual (Page 101)

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5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)
The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 57 and described in
Table 56 .
Figure 57. MAC Interrupt Mask Set Register (MACINTMASKSET)
31 16
Reserved
R-0
15 2 1 0
Reserved HOSTMASK STATMASK
R-0 R/W1S-0 R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset
Table 56. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTMASK 0-1 Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0 STATMASK 0-1 Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 58 and described in
Table 57 .
Figure 58. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
31 16
Reserved
R-0
15 2 1 0
Reserved HOSTMASK STATMASK
R-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n = value after reset
Table 57. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTMASK 0-1 Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0 STATMASK 0-1 Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
101 SPRUFL5B – April 2011 EMAC/MDIO Module
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