Texas Instruments TMS320C674X - Manual (Page 42)

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2.10.4 Hardware Receive QOS Support
Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifier
format and the associated Tag Control Information (TCI) format priority field. When the incoming frame
length/type value is equal to 81.00h, the EMAC recognizes the frame as an Ethernet Encoded Tag
Protocol Type. The two octets immediately following the protocol type contain the 16-bit TCI field. Bits
15-13 of the TCI field contain the received frames priority (0 to 7). The received frame is a low-priority
frame, if the priority value is 0 to 3; the received frame is a high-priority frame, if the priority value is 4 to 7.
All frames that have a length/type field value not equal to 81.00h are low-priority frames. Received frames
that contain priority information are determined by the EMAC as:
• A 48-bit (6 bytes) destination address equal to:
– The destination station's individual unicast address.
– The destination station's multicast address (MACHASH1 and MACHASH2).
– The broadcast address of all ones.
• A 48-byte (6 bytes) source address.
• The 16-bit (2 bytes) length/type field containing the value 81.00h.
• The 16-bit (2 bytes) TCI field with the priority field in the upper 3 bits.
• Data bytes
• The 4 bytes CRC.
The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) and the receive channel
n free buffer count registers (RXnFREEBUFFER) are used in conjunction with the priority information to
implement receive hardware QOS. Low-priority frames are filtered if the number of free buffers
(RXnFREEBUFFER) for the frame channel is less than or equal to the filter low threshold
(RXFILTERLOWTHRESH) value. Hardware QOS is enabled by the RXQOSEN bit in the receive
multicast/broadcast/promiscuous channel enable register (RXMBPENABLE).
2.10.5 Host Free Buffer Tracking
The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, and
promiscuous), if receive QOS or receive flow control is used. Disabled channel free buffer values are do
not cares. During initialization, the host should write the number of free buffers for each enabled channel
to the appropriate receive channel n free buffer count registers (RXnFREEBUFFER). The EMAC
decrements the appropriate channel’s free buffer value for each buffer used. When the host reclaims the
frame buffers, the host should write the channel free buffer register with the number of reclaimed buffers
(write to increment). There are a maximum of 65,535 free buffers available. RXnFREEBUFFER only
needs to be updated by the host if receive QOS or flow control is used.
2.10.6 Receive Channel Teardown
The host commands a receive channel teardown by writing the channel number to the receive teardown
register (RXTEARDOWN). When a teardown command is issued to an enabled receive channel, the
following occurs:
•
Any current frame in reception completes normally.
• The TDOWNCMPLT flag is set in the next buffer descriptor in the chain, if there is one.
• The channel head descriptor pointer is cleared to 0.
• A receive interrupt for the channel is issued to the host.
• The corresponding receive channel n completion pointer register (RXnCP) contains the value FFFF
FFCh.
Channel teardown may be commanded on any channel at any time. The host is informed of the teardown
completion by the set teardown complete (TDOWNCMPLT) buffer descriptor bit. The EMAC does not
clear any channel enables due to a teardown command. A teardown command to an inactive channel
issues an interrupt that software should acknowledge with an FFFF FFFCh acknowledge value to RXnCP
(note that there is no buffer descriptor in this case). Software may read RXnCP to determine if the
interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a
teardown command.
42 EMAC/MDIO Module SPRUFL5B – April 2011
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