Document Outline

• TMS320C674x/OMAP-L1x ProcessorEthernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module
  • Table of Contents
  • Preface
  • 1 Introduction
    • 1.1 Purpose of the Peripheral
    • 1.2 Features
    • 1.3 Functional Block Diagram
    • 1.4 Industry Standard(s) Compliance Statement
  • 2 Architecture
    • 2.1 Clock Control
    • 2.2 Memory Map
    • 2.3 Signal Descriptions
      • 2.3.1 Media Independent Interface (MII) Connections
      • 2.3.2 Reduced Media Independent Interface (RMII) Connections
    • 2.4 Ethernet Protocol Overview
      • 2.4.1 Ethernet Frame Format
      • 2.4.2 Ethernet’s Multiple Access Protocol
    • 2.5 Programming Interface
      • 2.5.1 Packet Buffer Descriptors
      • 2.5.2 Transmit and Receive Descriptor Queues
      • 2.5.3 Transmit and Receive EMAC Interrupts
      • 2.5.4 Transmit Buffer Descriptor Format
        • 2.5.4.1 Next Descriptor Pointer
        • 2.5.4.2 Buffer Pointer
        • 2.5.4.3 Buffer Offset
        • 2.5.4.4 Buffer Length
        • 2.5.4.5 Packet Length
        • 2.5.4.6 Start of Packet (SOP) Flag
        • 2.5.4.7 End of Packet (EOP) Flag
        • 2.5.4.8 Ownership (OWNER) Flag
        • 2.5.4.9 End of Queue (EOQ) Flag
        • 2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag
        • 2.5.4.11 Pass CRC (PASSCRC) Flag
      • 2.5.5 Receive Buffer Descriptor Format
        • 2.5.5.1 Next Descriptor Pointer
        • 2.5.5.2 Buffer Pointer
        • 2.5.5.3 Buffer Offset
        • 2.5.5.4 Buffer Length
        • 2.5.5.5 Packet Length
        • 2.5.5.6 Start of Packet (SOP) Flag
        • 2.5.5.7 End of Packet (EOP) Flag
        • 2.5.5.8 Ownership (OWNER) Flag
        • 2.5.5.9 End of Queue (EOQ) Flag
        • 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag
        • 2.5.5.11 Pass CRC (PASSCRC) Flag
        • 2.5.5.12 Jabber Flag
        • 2.5.5.13 Oversize Flag
        • 2.5.5.14 Fragment Flag
        • 2.5.5.15 Undersized Flag
        • 2.5.5.16 Control Flag
        • 2.5.5.17 Overrun Flag
        • 2.5.5.18  Code Error (CODEERROR) Flag
        • 2.5.5.19  Alignment Error (ALIGNERROR) Flag
        • 2.5.5.20  CRC Error (CRCERROR) Flag
        • 2.5.5.21  No Match (NOMATCH) Flag
    • 2.6 EMAC Control Module
      • 2.6.1 Internal Memory
      • 2.6.2 Bus Arbiter
      • 2.6.3 Interrupt Control
    • 2.7 MDIO Module
      • 2.7.1 MDIO Module Components
        • 2.7.1.1 MDIO Clock Generator
        • 2.7.1.2 Global PHY Detection and Link State Monitoring
        • 2.7.1.3 Active PHY Monitoring
        • 2.7.1.4 PHY Register User Access
      • 2.7.2 MDIO Module Operational Overview
        • 2.7.2.1 Initializing the MDIO Module
        • 2.7.2.2 Writing Data To a PHY Register
        • 2.7.2.3 Reading Data From a PHY Register
        • 2.7.2.4 Example of MDIO Register Access Code
    • 2.8 EMAC Module
      • 2.8.1 EMAC Module Components
        • 2.8.1.1 Receive DMA Engine
        • 2.8.1.2 Receive FIFO
        • 2.8.1.3 MAC Receiver
        • 2.8.1.4 Transmit DMA Engine
        • 2.8.1.5 Transmit FIFO
        • 2.8.1.6 MAC Transmitter
        • 2.8.1.7 Statistics Logic
        • 2.8.1.8 State RAM
        • 2.8.1.9 EMAC Interrupt Controller
        • 2.8.1.10 Control Registers and Logic
        • 2.8.1.11 Clock and Reset Logic
      • 2.8.2 EMAC Module Operational Overview
    • 2.9 MAC Interface
      • 2.9.1 Data Reception
        • 2.9.1.1 Receive Control
        • 2.9.1.2 Receive Inter-Frame Interval
        • 2.9.1.3 Receive Flow Control
      • 2.9.2 Data Transmission
        • 2.9.2.1 Transmit Control
        • 2.9.2.2 CRC Insertion
        • 2.9.2.3 Adaptive Performance Optimization (APO)
        • 2.9.2.4 Interpacket-Gap (IPG) Enforcement
        • 2.9.2.5 Back Off
        • 2.9.2.6 Transmit Flow Control
        • 2.9.2.7 Speed, Duplex, and Pause Frame Support
    • 2.10 Packet Receive Operation
      • 2.10.1 Receive DMA Host Configuration
      • 2.10.2 Receive Channel Enabling
      • 2.10.3 Receive Address Matching
      • 2.10.4 Hardware Receive QOS Support
      • 2.10.5 Host Free Buffer Tracking
      • 2.10.6 Receive Channel Teardown
      • 2.10.7 Receive Frame Classification
      • 2.10.8 Promiscuous Receive Mode
      • 2.10.9 Receive Overrun
    • 2.11 Packet Transmit Operation
      • 2.11.1 Transmit DMA Host Configuration
      • 2.11.2 Transmit Channel Teardown
    • 2.12 Receive and Transmit Latency
    • 2.13 Transfer Node Priority
    • 2.14 Reset Considerations
      • 2.14.1 Software Reset Considerations
      • 2.14.2 Hardware Reset Considerations
    • 2.15 Initialization
      • 2.15.1 Enabling the EMAC/MDIO Peripheral
      • 2.15.2 EMAC Control Module Initialization
      • 2.15.3 MDIO Module Initialization
      • 2.15.4 EMAC Module Initialization
    • 2.16 Interrupt Support
      • 2.16.1 EMAC Module Interrupt Events and Requests
        • 2.16.1.1 Transmit Packet Completion Interrupts
        • 2.16.1.2 Receive Packet Completion Interrupts
        • 2.16.1.3 Statistics Interrupt
        • 2.16.1.4 Host Error Interrupt
        • 2.16.1.5 Receive Threshold Interrupts
      • 2.16.2 MDIO Module Interrupt Events and Requests
        • 2.16.2.1 Link Change Interrupt
        • 2.16.2.2 User Access Completion Interrupt
      • 2.16.3 Proper Interrupt Processing
      • 2.16.4 Interrupt Multiplexing
    • 2.17 Power Management
    • 2.18 Emulation Considerations
  • 3 EMAC Control Module Registers
    • 3.1 EMAC Control Module Revision ID Register (REVID)
    • 3.2 EMAC Control Module Software Reset Register (SOFTRESET)
    • 3.3 EMAC Control Module Interrupt Control Register (INTCONTROL)
    • 3.4 EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN-C2RXTHRESHEN)
    • 3.5 EMAC Control Module Interrupt Core Receive Interrupt Enable Registers (C0RXEN-C2RXEN)
    • 3.6 EMAC Control Module Interrupt Core Transmit Interrupt Enable Registers (C0TXEN-C2TXEN)
    • 3.7 EMAC Control Module Interrupt Core Miscellaneous Interrupt Enable Registers (C0MISCEN-C2MISCEN)
    • 3.8 EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT-C2RXTHRESHSTAT)
    • 3.9 EMAC Control Module Interrupt Core Receive Interrupt Status Registers (C0RXSTAT-C2RXSTAT)
    • 3.10 EMAC Control Module Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-C2TXSTAT)
    • 3.11 EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers (C0MISCSTAT-C2MISCSTAT)
    • 3.12 EMAC Control Module Interrupt Core Receive Interrupts Per Millisecond Registers (C0RXIMAX-C2RXIMAX)
    • 3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX)
  • 4 MDIO Registers
    • 4.1 MDIO Revision ID Register (REVID)
    • 4.2 MDIO Control Register (CONTROL)
    • 4.3 PHY Acknowledge Status Register (ALIVE)
    • 4.4 PHY Link Status Register (LINK)
    • 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
    • 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
    • 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
    • 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
    • 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
    • 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
    • 4.11 MDIO User Access Register 0 (USERACCESS0)
    • 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0)
    • 4.13 MDIO User Access Register 1 (USERACCESS1)
    • 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1)
  • 5 EMAC Module Registers
    • 5.1 Transmit Revision ID Register (TXREVID)
    • 5.2 Transmit Control Register (TXCONTROL)
    • 5.3 Transmit Teardown Register (TXTEARDOWN)
    • 5.4 Receive Revision ID Register (RXREVID)
    • 5.5 Receive Control Register (RXCONTROL)
    • 5.6 Receive Teardown Register (RXTEARDOWN)
    • 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
    • 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
    • 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)
    • 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
    • 5.11 MAC Input Vector Register (MACINVECTOR)
    • 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR)
    • 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
    • 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
    • 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)
    • 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
    • 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
    • 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
    • 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)
    • 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
    • 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
    • 5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
    • 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)
    • 5.24 Receive Maximum Length Register (RXMAXLEN)
    • 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)
    • 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
    • 5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH)
    • 5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER)
    • 5.29 MAC Control Register (MACCONTROL)
    • 5.30 MAC Status Register (MACSTATUS)
    • 5.31 Emulation Control Register (EMCONTROL)
    • 5.32 FIFO Control Register (FIFOCONTROL)
    • 5.33 MAC Configuration Register (MACCONFIG)
    • 5.34 Soft Reset Register (SOFTRESET)
    • 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)
    • 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)
    • 5.37 MAC Hash Address Register 1 (MACHASH1)
    • 5.38 MAC Hash Address Register 2 (MACHASH2)
    • 5.39 Back Off Test Register (BOFFTEST)
    • 5.40 Transmit Pacing Algorithm Test Register (TPACETEST)
    • 5.41 Receive Pause Timer Register (RXPAUSE)
    • 5.42 Transmit Pause Timer Register (TXPAUSE)
    • 5.43 MAC Address Low Bytes Register (MACADDRLO)
    • 5.44 MAC Address High Bytes Register (MACADDRHI)
    • 5.45 MAC Index Register (MACINDEX)
    • 5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP)
    • 5.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP)
    • 5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)
    • 5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP)
    • 5.50 Network Statistics Registers
      • 5.50.1 Good Receive Frames Register (RXGOODFRAMES)
      • 5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES)
      • 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES)
      • 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES)
      • 5.50.5 Receive CRC Errors Register (RXCRCERRORS)
      • 5.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS)
      • 5.50.7 Receive Oversized Frames Register (RXOVERSIZED)
      • 5.50.8 Receive Jabber Frames Register (RXJABBER)
      • 5.50.9 Receive Undersized Frames Register (RXUNDERSIZED)
      • 5.50.10 Receive Frame Fragments Register (RXFRAGMENTS)
      • 5.50.11 Filtered Receive Frames Register (RXFILTERED)
      • 5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED)
      • 5.50.13 Receive Octet Frames Register (RXOCTETS)
      • 5.50.14 Good Transmit Frames Register (TXGOODFRAMES)
      • 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)
      • 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES)
      • 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES)
      • 5.50.18 Deferred Transmit Frames Register (TXDEFERRED)
      • 5.50.19 Transmit Collision Frames Register (TXCOLLISION)
      • 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL)
      • 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL)
      • 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL)
      • 5.50.23 Transmit Late Collision Frames Register (TXLATECOLL)
      • 5.50.24 Transmit Underrun Error Register (TXUNDERRUN)
      • 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)
      • 5.50.26 Transmit Octet Frames Register (TXOCTETS)
      • 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64)
      • 5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127)
      • 5.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255)
      • 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)
      • 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023)
      • 5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP)
      • 5.50.33 Network Octet Frames Register (NETOCTETS)
      • 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)
      • 5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS)
      • 5.50.36 Receive DMA Overruns Register (RXDMAOVERRUNS)
  • Appendix A Glossary
  • Appendix B Revision History