Section 3.3 – Texas Instruments TMS320C674X User Manual

Page 59

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EMAC Control Module Registers

3.3

EMAC Control Module Interrupt Control Register (INTCONTROL)

The EMAC control module interrupt control register (INTCONTROL) is shown in

Figure 14

and described

in

Table 11

. The settings in the INTCONTROL register are used in conjunction with the CnRXIMAX and

CnTXIMAX registers.

Figure 14. EMAC Control Module Interrupt Control Register (INTCONTROL)

31

24

Reserved

R-0

23

22

21

20

19

18

17

16

Reserved

C2TXPACEEN

C2RXPACEEN

C1TXPACEEN

C1RXPACEEN

C0TXPACEEN

C0RXPACEEN

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

15

12

11

0

Reserved

INTPRESCALE

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. EMAC Control Module Interrupt Control Register (INTCONTROL)

Bit

Field

Value

Description

31-22

Reserved

0

Reserved

21

C2TXPACEEN

Enable pacing for TX interrupt pulse generation on Interrupt Core 2

0

Pacing for TX interrupts on Core 2 disabled.

1

Pacing for TX interrupts on Core 2 enabled.

20

C2RXPACEEN

Enable pacing for RX interrupt pulse generation on Interrupt Core 2

0

Pacing for RX interrupts on Core 2 disabled.

1

Pacing for RX interrupts on Core 2 enabled.

19

C1TXPACEEN

Enable pacing for TX interrupt pulse generation on Interrupt Core 1

0

Pacing for TX interrupts on Core 1 disabled.

1

Pacing for TX interrupts on Core 1 enabled.

18

C1RXPACEEN

Enable pacing for RX interrupt pulse generation on Interrupt Core 1

0

Pacing for RX interrupts on Core 1 disabled.

1

Pacing for RX interrupts on Core 1 enabled.

17

C0TXPACEEN

Enable pacing for TX interrupt pulse generation on Interrupt Core 0

0

Pacing for TX interrupts on Core 0 disabled.

1

Pacing for TX interrupts on Core 0 enabled.

16

C0RXPACEEN

Enable pacing for RX interrupt pulse generation on Interrupt Core 0

0

Pacing for RX interrupts on Core 0 disabled.

1

Pacing for RX interrupts on Core 0 enabled.

15-12

Reserved

0

Reserved

11-0

INTPRESCALE

0-7FFh

Number of internal EMAC module reference clock periods within a 4

μ

s time window (see

your device-specific data manual for information).

59

SPRUFL5B – April 2011

EMAC/MDIO Module

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