Texas Instruments TMS320C674X - Manual (Page 52)

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When the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing the
packet's last buffer descriptor address to the appropriate channel queue's receive completion pointer
located in the state RAM block. The interrupt is generated by the write when enabled by the interrupt
mask, regardless of the value written.
Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then
acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the
queue's associated receive completion pointer in the receive DMA state RAM.
The data written by the host (buffer descriptor address of the last processed buffer) is compared to the
data in the register written by the EMAC (address of last buffer descriptor used by the EMAC). If the two
values are not equal (which means that the EMAC has received more packets than the CPU has
processed interrupts for), the receive packet completion interrupt signal remains asserted. If the two
values are equal (which means that the host has processed all packets that the EMAC has received), the
pending interrupt is de-asserted. The value that the EMAC is expecting is found by reading the receive
channel n completion pointer register (RXnCP).
The EMAC write to the completion pointer actually stores the value in the state RAM. The CPU written
value does not actually change the register value. The host written value is compared to the register
content (which was written by the EMAC) and if the two values are equal then the interrupt is removed;
otherwise, the interrupt remains asserted. The host may process multiple packets prior to acknowledging
an interrupt, or the host may acknowledge interrupts for every packet.
The application software must acknowledge the EMAC control module after processing packets by writing
the appropriate CnTX key to the EMAC End-Of-Interrupt Vector register (MACEOIVECTOR). See
Section 5.12 for the acknowledge key values.
2.16.1.3 Statistics Interrupt
The statistics level interrupt (STATPEND) is issued when any statistics value is greater than or equal to
8000 0000h, if enabled by setting the STATMASK bit in the MAC interrupt mask set register
(MACINTMASKSET) to 1. The statistics interrupt is removed by writing to decrement any statistics value
greater than 8000 0000h. As long as the most-significant bit of any statistics value is set, the interrupt
remains asserted.
The application software must akcnowledge the EMAC control module after receiving statistics interrupts
by writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector register (MACEOIVECTOR).
See
Section 5.12 for the acknowledge key values.
2.16.1.4 Host Error Interrupt
The host error interrupt (HOSTPEND) is issued, if enabled, under error conditions dealing with the
handling of buffer descriptors, detected during transmit or receive DMA transactions. The failure of the
software application to supply properly formatted buffer descriptors results in this error. The error bit can
only be cleared by resetting the EMAC module in hardware.
The host error interrupt is enabled by setting the HOSTMASK bit in the MAC interrupt mask set register
(MACINTMASKSET) to 1. The host error interrupt is disabled by clearing the appropriate bit by writing a 1
in the MAC interrupt mask clear register (MACINTMASKCLEAR). The raw and masked host error interrupt
status may be read by reading the MAC interrupt status (unmasked) register (MACINTSTATRAW) and the
MAC interrupt status (masked) register (MACINTSTATMASKED), respectively.
The transmit host error conditions are:
•
SOP error
• Ownership bit not set in SOP buffer
• Zero next buffer descriptor pointer with EOP
• Zero buffer pointer
• Zero buffer length
• Packet length error
52 EMAC/MDIO Module SPRUFL5B – April 2011
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