Texas Instruments TMS320C674X - Manual (Page 53)

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The receive host error conditions are:
•
Ownership bit not set in input buffer
• Zero buffer pointer
The application software must acknowledge the EMAC control module after receiving host error interrupts
by writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See
Section 5.12 for the acknowledge key values.
2.16.1.5 Receive Threshold Interrupts
Each of the eight receive channels have a corresponding receive threshold interrupt (RXnTHRESHPEND).
The receive threshold interrupts are level interrupts that remain asserted until the triggering condition is
cleared by the host. Each of the eight threshold interrupts may be individually enabled by setting to 1 the
appropriate bit in the RXINTMASKSET register. Each of the eight channel interrupts may be individually
disabled by clearing to zero the appropriate bit by writing a 1 in the receive interrupt mask clear register
(RXINTMASKCLEAR). The raw and masked interrupt receive interrupt status may be read by reading the
receive interrupt status (unmasked) register (RXINTSTATRAW) and the receive interrupt status (masked)
register (RXINTSTATMASKED),respectively.
An RXnTHRESHPEND interrupt bit is asserted when enabled and when the channel’s associated free
buffer count (RXnFREEBUFFER) is less than or equal to the channel’s associated flow control threshold
register (RXnFLOWTHRESH). The receive threshold interrupts use the same free buffer count and
threshold logic as does flow control, but the interrupts are independently enabled from flow control. The
threshold interrupts are intended to give the host an indication that resources are running low for a
particular channel(s).
The applications software must acknowledge the EMAC control module after receiving threshold interrupts
by writing the appropriate CnRXTHRESH key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR).
See
Section 5.12 for the acknowledge key values.
2.16.2 MDIO Module Interrupt Events and Requests
The MDIO module generates two interrupt events:
•
LINKINT0: Serial interface link change interrupt. Indicates a change in the state of the PHY link
selected by the USERPHYSEL0 register
• USERINT0: Serial interface user command event complete interrupt selected by the USERACCESS0
register
2.16.2.1 Link Change Interrupt
The MDIO module asserts a link change interrupt (LINKINT0) if there is a change in the link state of the
PHY corresponding to the address in the PHYADRMON bit in the MDIO register USERPHYSEL0, and if
the LINKINTENB bit is also set in USERPHYSEL0. This interrupt event is also captured in the
LINKINTRAW bit in the MDIO link status change interrupt register (LINKINTRAW). LINKINTRAW bits 0
and 1 correspond to USERPHYSEL0 and USERPHYSEL1, respectively.
When the interrupt is enabled and generated, the corresponding LINKINTMASKED bit is also set in the
MDIO link status change interrupt register (LINKINTMASKED). The interrupt is cleared by writing back the
same bit to LINKINTMASKED (write to clear).
The application software must acknowledge the EMAC control module after receiving MDIO interrupts by
writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See
Section 5.12 for the acknowledge key values.
53 SPRUFL5B – April 2011 EMAC/MDIO Module
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