Texas Instruments TMS320C674X - Manual (Page 54)

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2.16.2.2 User Access Completion Interrupt
When the GO bit in one of the MDIO register USERACCESS0 transitions from 1 to 0 (indicating
completion of a user access) and the corresponding USERINTMASKSET bit in the MDIO user command
complete interrupt mask set register (USERINTMASKSET) corresponding to USERACCESS0 is set, a
user access completion interrupt (USERINT) is asserted. This interrupt event is also captured in the
USERINTRAW bit in the MDIO user command complete interrupt register (USERINTRAW).
USERINTRAW bits 0 and bit 1 correspond to USERACCESS0 and USERACCESS1, respectively.
When the interrupt is enabled and generated, the corresponding USERINTMASKED bit is also set in the
MDIO user command complete interrupt register (USERINTMASKED). The interrupt is cleared by writing
back the same bit to USERINTMASKED (write to clear).
The application software must acknowledge the EMAC control module after receiving MDIO interrupts by
writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See
Section 5.12 for the acknowledge key values.
2.16.3 Proper Interrupt Processing
All the interrupts signaled from the EMAC and MDIO modules are level driven, so if they remain active,
their level remains constant; the CPU core may require edge- or pulse-triggered interrupts. In order to
properly convert the level-driven interrupt signal to an edge- or pulse-triggered signal, the application
software must make use of the interrupt control logic contained in the EMAC control module.
Section 2.6.3 discusses the interrupt control contained in the EMAC control module. For safe interrupt
processing, upon entry to the ISR, the software application should disable interrupts using the EMAC
control module registers CnRXTHRESHEN, CnRXEN, CnTXEN, CnMISCEN, and then reenable them
upon leaving the ISR. If any interrupt signals are active at that time, this creates another rising edge on
the interrupt signal going to the CPU interrupt controller, thus triggering another interrupt. The EMAC
control module also uses the EMAC control module registers INTCONTROL, CnTXIMAX, and CnRXIMAX
to implement interrupt pacing. The application software must acknowledge the EMAC control module by
writing the appropriate key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See
Section 5.12 for
the acknowledge key values.
2.16.4 Interrupt Multiplexing
The EMAC control module combines different interrupt signals from both the EMAC and MDIO modules
into four interrupt signals (CnRXTHRESHPULSE, CnRXPULSE, CnTXPULSE, CnMISCPULSE) that are
routed to three independent interrupt cores in the control module. Each interrupt core is capable of
relaying all four interrupt signals out of the control module. Some devices may have an individual interrupt
core dedicated to a specific CPU or interrupt controller. This configuration gives users of devices greater
flexibility when allocating system resources for EMAC management.
When an interrupt is generated, the reason for the interrupt can be read from the MAC input vector
register (MACINVECTOR) located in the EMAC memory map. MACINVECTOR combines the status of the
following 28 interrupt signals: TXPENDn, RXPENDn, RXTHRESHPENDn, STATPEND, HOSTPEND,
LINKINT0, and USERINT0.
For more details on the interrupt mapping, see your device-specific System Reference Guide.
54 EMAC/MDIO Module SPRUFL5B – April 2011
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