Texas Instruments TMS320C674X - Manual (Page 78)

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4.10 MDIO User Command Complete Interrupt Mask Clear Register
(USERINTMASKCLEAR)
The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in
Figure 34 and described in Table 32 .
Figure 34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
31 16
Reserved
R-0
15 2 1 0
Reserved USERACCESS1 USERACCESS0
R-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n = value after reset
Table 32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 USERACCESS1 MDIO user command complete interrupt mask clear for USERINTMASKED[1]. Setting the bit to
1 will disable further user command complete interrupts for USERACCESS1. Writing a 0 to this
bit has no effect.
0 MDIO user command complete interrupts for the MDIO user access register USERACCESS1 is
enabled.
1 MDIO user command complete interrupts for the MDIO user access register USERACCESS1 is
disabled.
0 USERACCESS0 MDIO user command complete interrupt mask clear for USERINTMASKED[0]. Setting the bit to
1 will disable further user command complete interrupts for USERACCESS0. Writing a 0 to this
bit has no effect.
0 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is
enabled.
1 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is
disabled.
78 EMAC/MDIO Module SPRUFL5B – April 2011
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