Cirrus Logic CS485xx - Manual (Page 15)

1-7 Copyright 2009 Cirrus Logic, Inc. DS734UM7
Functional Overview of the CS485xx Chip
CS485xx Hardware User’s Manual
buffers which are 32 bits wide. The O/S can dedicate DMA channels to fill the DAO data buffers from
memory. DAO control is handled through the peripheral bus.
1.3.4 Digital Audio Input (DAI) Controller
The CS485xx Digital Audio Input (DAI) controller can operate with a single clock domain or in a dual-clock-
domain mode. In the dual-clock-domain mode, there are two SCLKs and two LRCLKs and up to five serial
audio input pins which can accept up to 10 channels of audio data. In single-clock-domain mode there is
only one SCLK and one LRCLK, but there are up to six serial audio input pins which can accept up to 12
channels of audio data.
DAI control is handled through the peripheral bus. Each DAI pin can be configured to load audio samples in
a variety of formats. In addition to accepting multiple formats, the DAI controller has the ability to accept
multiple stereo channels on a single DAI_DATAx pin. All six DAI data pins are slaves and normally use the
DAI clock pins, but they may also be reconfigured to use the DAO serial output clock pins (DAO_SCLK and
DAO_LRCLK). A single global configuration register provides a set of enable bits to ensure that ports may
be started synchronously.
1.3.5 Direct Stream Digital (DSD) Controller
The CS48560 also has a DSD controller which allows the DSP to be integrated into a system that supports
SACD audio. The DSD data pins are multiplexed with the DAI1 pins. The DSD port consists of a bit clock
(DSD_CLK) and up to six DSD data inputs (DSD[5:0]).
1.3.6 General Purpose I/O
A 17-bit, general-purpose I/O (GPIO) port is provided on the CS485xx chip to enhance system flexibility.
Many of the functional pins can be used for either GPIO or other peripheral functions.
Each GPIO pin can be individually configured as an output, an input, or an input with interrupt. A GPIO
interrupt can be triggered on a rising edge (0-to-1 transition), falling edge (1-to-0 transition), or logic level
(either 0 or 1). Each pin configured as an input with interrupt can be assigned its own interrupt trigger
condition. All GPIOs share a common interrupt vector.
1.3.7 Serial Control Ports (SPI ™ or I 2 C ™ Standards)
The CS485xx has a serial control port (SCP) that supports SPI
™
and I
2
C
™
Master/Slave communication
modes. The serial control port allows external devices such as microcontrollers and serial FLASH to
communicate with the CS485xx chip through either I
2
C or SPI serial communication standards.
The CS485xx SPI and I
2
C serial communication protocols are identical from a functional standpoint. The
main difference between the two is the protocol being implemented between the CS485xx and the external
device. In addition, the I
2
C slave has a true I
2
C mode that utilizes data-flow mechanisms inherent to the I
2
C
protocol. If this mode is enabled, the I
2
C slave will hold SCP_CLK low to delay a transfer as needed.
The communication protocol (SPI or I
2
C) and mode (master or slave) is selected by the state of the HS[3:0]
pins at the rising edge of RESET.
The serial clock pin can support frequencies as high as 25 MHz in SPI mode.
The CS485xx has two additional serial communication pins not specified in either the I 2 C or SPI
specification. The port uses the SCP_IRQ pin to indicate that a read message is ready for the host. The port
uses the SCP_BSY pin to warn the host to pause communication.