2 left-justified format, 3 dai hardware configuration, 1 dai hardware naming convention – Cirrus Logic CS485xx User Manual

Page 60

Advertising
background image

DAI Hardware Configuration

CS485xx Hardware User’s Manual

DS734UM7

Copyright 2009 Cirrus Logic, Inc.

4-6

Figure 4-5. I

2

S format (Rising Edge Valid SCLK)

4.2.3.2 Left-Justified Format

Figure 4-6

illustrates the left-justified format with a rising-edge DAIn_SCLK. Data is presented most-

significant bit first on the first DAIn_SCLK after a DAIn_LRCLK transition and is valid on the rising edge of
DAIn_SCLK. For the left-justified format, the left subframe is presented when DAIn_LRCLK is high and the
right subframe is presented when DAIn_LRCLK is low. The left-justified format can also be programmed for
data to be valid on the falling edge of DAIn_SCLK.

Figure 4-6. Left-justified Format (Rising Edge Valid SCLK)

4.3 DAI Hardware Configuration

After code download or soft reset, and before kickstarting the application, the host has the option of
changing the default hardware configuration. (Please see AN298, CS485xx Firmware User’s Manual” for
more information on kickstarting). In general, the hardware configuration can only be changed immediately
after download or after soft reset.

Hardware configuration messages are used to physically reconfigure the hardware of the audio decoder, as
when enabling or disabling address checking for the serial communication port. Hardware configuration

messages are also used to initialize the format (e.g., I

2

S, left justified, etc.) for digital data inputs, as well as

the data format and clocking options for the digital output port.

4.3.1 DAI Hardware Naming Convention

The naming convention of the input hardware configuration is as follows:

INPUT A B C D E F G H

Where A, B, C, D, E, F, G, and H are the parameters used to fully define the input port. The parameters are
defined as follows:

A - Data Format

B - SCLK Polarity

C - LRCLK Polarity.

DAIn_LRCLK

DAIn_SCLK

Left Channel

Right Channel

DAI_DATA

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

DAIn_LRCLK

DAIn_SCLK

L eft C h a n nel

Rig ht C h a n n el

DAIn_DATA

+3

+2

+1

LSB

+5

+4

MSB

-1

-2

-3

-4

-5

+3

+2

+1

+5

+4

-1

-2

-3

-4

LSB

MSB

Advertising