Cirrus Logic CS485xx - Manual (Page 50)

SPI Port
CS485xx Hardware User’s Manual
DS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-18
Figure 3-15. SPI Write Flow Diagram
3.3.1.3.1 SPI Write Protocol Procedure
1. A SPI transfer is initiated when the chip select SCP_CS is driven low. SCP_CS driven low indicates
that CS485xx is in SPI slave mode.
2. This is followed by a 7-bit address and the read/write bit set low for a write. So, the master should
send 0x80. The 0x80 byte represents the 7-bit SPI address 1000000b, and the least significant bit set
to ‘0’, designates a write.
3. The master should then clock the 4-byte data word into the slave device, most-significant bit first, one
byte at a time. The data byte is transferred to the CS485xx DSP (slave) on the falling edge of the
eighth serial clock. For this reason, the serial clock should be held low so that eight transitions from
low-to-high-to-low will occur for each byte.
4. If the master has no more data words to write to the CS485xx, then proceed to step 6. If the master
has more data words to write to the CS485xx, then proceed to step 5.
5. The master should poll the SCP_BSY signal until it goes high. If the SCP_BSY signal is low, it
indicates that the CS485xx is busy performing some task that requires halting the serial control port.
Once the CS485xx is able to receive more data words, the SCP_BSY signal will go high. Once the
SCP_BSY signal is high, proceed to step 3.
6. The master finishes the SPI write transaction by driving the CS485xx SCP_CS signal high.
3.3.1.4 Performing a Serial SPI Read
Information provided in this section is intended as a functional description indicating how an external device
(Master) performs an SPI read from the CS485xx (slave). The system designer must ensure that all timing
constraints of the SPI read cycle are met (see the CS485xx datasheet for timing specifications).
SPI START: SCP_CS
(LOW)
WRITE ADDRESS BYTE
0x80
MORE DATA?
Y
N
WRITE 4 DATA BYTES
SPI STOP: SCP_CS
(HIGH)
SCP_BSY
(LOW)?
N
Y