Cirrus Logic CS485xx - Manual (Page 4)

iv Copyright 2009 Cirrus Logic DS734UM7
Contents
CS485xx Hardware User’s Manual
3.2.2.1 I
2
C Bus Dynamics..........................................................................................3-4
3.2.2.2 I
2
C Messaging ...............................................................................................3-7
3.2.2.3 Performing a Serial I 2
C Write ........................................................................3-7
3.2.2.4 Performing a Serial I
2
C Read ........................................................................3-9
3.3 SPI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
3.3.1 SPI System Bus Description.........................................................................................3-14
3.3.1.1 SPI Bus Dynamics .......................................................................................3-15
3.3.1.2 SPI Messaging.............................................................................................3-17
3.3.1.3 Performing a Serial SPI Write ......................................................................3-17
3.3.1.4 Performing a Serial SPI Read......................................................................3-18
Chapter 4. Digital Audio Input Interface .............................................................. 4-1
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.2 Digital Audio Input Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.2.1 DAI Pin Description ........................................................................................................4-2
4.2.2 Supported DAI Functional Blocks...................................................................................4-3
4.2.2.1 Dual Clock Domain - 10 Channel Input .........................................................4-3
4.2.2.2 Single Clock Domain - 12 Channel Input .......................................................4-4
4.2.3 Digital Audio Formats .....................................................................................................4-5
4.2.3.1 I
2
S Format .....................................................................................................4-5
4.2.3.2 Left-Justified Format ......................................................................................4-6
4.3 DAI Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
4.3.1 DAI Hardware Naming Convention ................................................................................4-6
Chapter 5. Direct Stream Data (DSD) Input Interface ......................................... 5-1
5.1 Digital Audio Input Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.1.1 DSD Pin Description.......................................................................................................5-1
5.1.2 Supported DSD Functional Blocks .................................................................................5-1
Chapter 6. Digital Audio Output Interface ........................................................... 6-1
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.2 Digital Audio Output Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.2.1 DAO Pin Description.......................................................................................................6-1
6.2.2 Supported DAO Functional Blocks .................................................................................6-4
6.2.3 DAO Interface Formats...................................................................................................6-4
6.2.3.1 I
2
S Format .....................................................................................................6-4
6.2.3.2 Left-Justified Format ......................................................................................6-4
6.2.3.3 One-line Data Mode Format (Multichannel)...................................................6-5
6.2.4 DAO Hardware Configuration.........................................................................................6-5
6.2.5 S/PDIF Transmitter.........................................................................................................6-9
Chapter 8. General Purpose Input/Output Pins .................................................. 7-1
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7.2 GPIO Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7.3 Watchdog Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2
Chapter 8. System Integration.............................................................................. 8-1
8.1 Typical Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-10
8.2.1 Power and Ground .......................................................................................................8-10
8.2.1.1 Power...........................................................................................................8-10