Cirrus Logic CS485xx - Manual (Page 17)

1-9 Copyright 2009 Cirrus Logic, Inc. DS734UM7
Functional Overview of the CS485xx Chip
CS485xx Hardware User’s Manual
1.3.13 Programmable Interrupt Controller
The Programmable Interrupt Controller (PIC) forces all incoming interrupts to be synchronized to the global
clock, HCLK. The PIC provides up to 16 interrupts to the DSP Core. The interrupts are prioritized with
interrupt 0 as the highest priority and interrupt 15 as the lowest priority. Each interrupt has a corresponding
interrupt address that is also supplied to the DSP core. The interrupt address is the same as the IRQ number
(interrupt 0 uses interrupt address 0 and interrupt 15 uses interrupt address 15). Both an enable mask and a
run mask are provided for each interrupt. The enable mask allows the enabled interrupts to generate a
PIC_REQ signal to the DSP core, and the run mask allows the enabled interrupts to generate a PIC_CLR,
thereby bringing the core out of its halt state when it accepts the interrupt.
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