2 single clock domain - 12 channel input – Cirrus Logic CS485xx User Manual

Page 58

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Digital Audio Input Port Description

CS485xx Hardware User’s Manual

DS734UM7

Copyright 2009 Cirrus Logic, Inc.

4-4

Figure 4-3. 6-Channel DAI Port Block Diagram

Currently supported are 4 lines of linear PCM input (DAI1_DATA3:0) on the first clock domain and 1
additional line of linear PCM (DAI2_DATA0) on the second clock domain, which will support up to 10
channels of PCM. These two input ports can have separate clock domains, or share a single clock domain.
The firmware currently available can operate on only one of these input ports at a time, providing for stereo
PCM processing or multichannel PCM processing. Please see AN298 for details on configuring the firmware
to select these different inputs.

4.2.2.2 Single Clock Domain - 12 Channel Input

The DAI can also be configured to accept up to 12 channels of linear PCM audio (6 serial audio data inputs)
by converting DAI1_LRCLK into a data pin (DAI1_DATA5). Consequently, there is only one possible clock
domain (DAI2_LRCLK/SCLK).

DAI1_DATA0

D

M

A t

o

Peri

pheral Bus

DAI1_DATA0

DAI2_DATA0

DAI2_DATA0

DAI_LRCLK1
DAI_SCLK1

DAI_LRCLK2
DAI_SCLK2

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