Cirrus Logic CS485xx - Manual (Page 16)

Functional Overview of the CS485xx Chip
CS485xx Hardware User’s Manual
DS734UM7 Copyright 2009 Cirrus Logic, Inc. 1-8
1.3.8 Serial Flash Controller
The CS485xx boot ROM supports a protocol that allows autoboot from a serial Flash or EEPROM device.
Boot modes are supported for 13-bit addressing, 16-bit addressing, and 20-bit addressing. A dedicated
FLASH/EEPROM (EE_CS) chip select pin allows Flash devices to be connected without additional chip
select logic.
1.3.9 DMA Controller
The DMA controller contains 8 channels. The O/S uses 3 channels, 2 for the DAO, and 1 for the DAI. The
DMA block is able to move data to/from X or Y memory, or alternate between both X and Y memory. The
DMA controller moves data to/from X and/or Y memory opportunistically (if the core is not currently
accessing that particular memory space during the current cycle). The DMA controller has a “Dead Man’s”
timer so that if the core is running an inner loop and accessing memory every cycle, the DMA controller can
interrupt the core to run a DMA cycle.
1.3.10 Internal Timers
Two identical 32-bit timer blocks run off the CS485xx DSP clock. The timer count decrements with each
clock tick of the DSP clock when the timer is enabled. When the timer count reaches zero, it is re-initialized,
and may be programmed to generate an interrupt to the DSP.
1.3.11 Watchdog Timer
The CS485xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog
timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral
ensures that the CS485xx will reset itself in the event of a temporary system failure. In standalone mode
(that is, no host microcontroller (MCU) is present), the DSP will reboot from external FLASH. In slave mode
(that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and the
DSP should be rebooted and reconfigured.
1.3.12 Clock Manager and PLL
The CS485xx Clock Manager and PLL module contains an Analog PLL, RTL Clock Synthesizer, and Clock
Manager. The Analog PLL is a customized analog hard macro that contains the Phase Detector (PD),
Charge Pump, Loop Filter, VCO, and other non-digital PLL logic. The Clock Synthesizer is a digital design
wrapper around the analog PLL that allows clock frequency ranges to be programmed. The Clock Manager
is a digital design wrapper for the Clock Synthesizer that provides the logic (control registers) necessary to
meet chip clocking requirements.
The Clock Manager and PLL module generates two master clocks:
• HCLK - global chip clock (clocks the DSP core, internal memories, SDRAM, Flash, and all
peripherals)
• OVFS - oversampled audio clock. This clock feeds the DAO block which has dividers to generate
the DAO_MCLK, DAO_SCLK, and DAO_LRCLK.
The Clock Manager has the ability to bypass the PLL so that the HCLK will run directly off the PLL Reference
Clock (REFCLK). While operating in this mode, the OVFS clock can still be divided off the VCO so the PLL
can be tested.
A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is
selectable between 1:1 (default) or 2:1.