Cirrus Logic CS485xx - Manual (Page 7)

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Tables
CS485xx Hardware User’s Manual
Tables
Table 1-1. List of Available Firmware Modules and Associated Application Note. .......................................1-4
Table 1-2. Device and Firmware Selection Guide ........................................................................................1-7
Table 2-1. Operation Modes .........................................................................................................................2-2
Table 2-2. SLAVE_BOOT message for CS485xx ........................................................................................2-6
Table 2-3. SOFT_RESET message for CS485xx ........................................................................................2-6
Table 2-4. Boot Read Messages from CS485xx ..........................................................................................2-6
Table 2-5. Boot Command Messages for CS485xx .....................................................................................2-7
Table 2-6. SOFTBOOT Message .................................................................................................................2-8
Table 2-7. SOFTBOOT_ACK Message .......................................................................................................2-8
Table 2-8. wakeup_uld Options and Values................................................................................................2-14
Table 3-1. Serial Control Port 1 I
2
C Signals .................................................................................................3-4
Table 3-2. Serial Control Port SPI Signals .................................................................................................3-14
Table 4-1. Digital Audio Input Port ...............................................................................................................4-2
Table 4-2. Input Data Format Configuration (Input Parameter A) ................................................................4-7
Table 4-3. Input SCLK Polarity Configuration (Input Parameter B) ..............................................................4-8
Table 4-4. Input LRCLK Polarity Configuration (Input Parameter C) ...........................................................4-8
Table 4-5. DAI2_DATA Clock Source (Input Parameter E) ..........................................................................4-9
Table 4-6. DAI1_DATA Clock Source (Input Parameter F) ..........................................................................4-9
Table 4-7. Chip Version (Input Parameter G) ..............................................................................................4-9
Table 4-8. DAII TDM (Input Parameter H) ....................................................................................................4-9
Table 5-1. DSDl Audio Input Port .................................................................................................................5-1
Table 6-1. Digital Audio Output (DAO) Pins .................................................................................................6-1
Table 6-2. Output Clock Mode Configuration (Parameter A) .......................................................................6-5
Table 6-3. DAO1 & DAO2 Clocking Relationship Configuration (Parameter B) ...........................................6-6
Table 6-4. Output DAO_SCLK/LRCLK Configuration (Parameter C) ..........................................................6-6
Table 6-5. Output Data Format Configuration (Parameter D) ......................................................................6-8
Table 6-6. Output DAO_LRCLK Polarity Configuration (Parameter E) ........................................................6-9
Table 6-7. Output DAO_SCLK Polarity Configuration (Parameter F) ..........................................................6-9
Table 6-8. DAO TDM (Parameter G) ............................................................................................................6-9
Table 6-9. S/PDIF Transmitter Pins ...........................................................................................................6-10
Table 6-10. S/PDIF Transmitter Configuration ...........................................................................................6-10
Table 7-1. Digital Audio Output (DAO) Pins .................................................................................................7-1
Table 8-1. Core Supply Pins ......................................................................................................................8-10
Table 8-2. I/O Supply Pins .........................................................................................................................8-10
Table 8-3. Core and I/O Ground Pins .........................................................................................................8-11
Table 8-4. PLL Supply Pins ........................................................................................................................8-11