Cirrus Logic CS485xx - Manual (Page 68)

Digital Audio Output Port Description
CS485xx Hardware User’s Manual
DS734UM7 Copyright 2009 Cirrus Logic, Inc. 6-2
DAO_MCLK is the master clock and is firmware configurable to be either an input (slave) or an output
(master). If MCLK is to be used as an output, the internal PLL must be used. As an output MCLK can be
configured to provide a 128Fs, 256Fs, or 512Fs clock, where Fs is the output sample rate.
• DAO_SCLK is the bit clock used to clock data out on DAOn_DATA[n].
• DAO_LRCLK is the data framing clock whose frequency is equal to the sampling frequency for the
DAO data outputs.
• DAOn_DATA[n] are the data outputs and are typically configured for outputting two channels of I
2
S
or left-justified PCM data.
.
Figure 6-1. CS48560 DAO Block Diagram
DAO1_DATA0
P
e
ri
ph
er
a
l B
u
s
to
D
M
A
DAO1_DATA1
DAO1_DATA2
DAO1_DATA3
DAO1_DATA3, XMTA
DAO2_DATA0
DAO2_DATA1
Cl
oc
k
M
a
na
ge
r
DAO_MCLK
DAO_SCLK
DAO_LRCLK
SPDIF
ENCODER