Cirrus Logic CS485xx - Manual (Page 49)

3-17 Copyright 2009 Cirrus Logic, Inc. DS734UM7
SPI Port
CS485xx Hardware User’s Manual
3.3.1.2 SPI Messaging
Messaging to the CS485xx using the SPI bus requires usage of all the information provided in the SPI Bus
Description and Bus Dynamics above. For control and application image downloading, SPI transactions to
the CS485xx will involve 4-byte words. A detailed description of the serial SPI communication mode is
provided in this section. This includes:
• A flow diagram and description for a serial SPI write
• A flow diagram and description for a serial SPI read
3.3.1.3 Performing a Serial SPI Write
Information provided in this section is intended as a functional description indicating how to perform an SPI
write from an external device (master) to the CS485xx DSP (slave). The system designer must ensure that
all timing constraints of the SPI Write Cycle are met (see the CS485xx datasheet for timing specifications).
When performing an SPI write, the same protocol is used whether writing single-word messages to the boot
firmware, writing multiple-word overlay images to the boot firmware, or writing multiple-word messages to
the application firmware. The example shown in this section can be generalized to fit any SPI write situation.
The flow diagram shown in Figure 3-15 , illustrates the sequence of events that define the SPI write protocol.
This protocol is discussed in the high-level procedure in Section 3.3.1.3.1 .
SCP_CLK
SCP_MOSI 7-bit SPI Address Data Byte
SCP_CS
R/W
SCP_CLK
SCP_MOSI
Data Byte
SCP_CS
SCP_MISO
R/W 7-bit SPI Address