Cirrus Logic CS4953xx - Manual (Page 103)

144-Pin LQFP Pin Assigments
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 9-15
9.5 144-Pin LQFP Pin Assigments
Figure 9-11 shows the 144-Pin LQFP Pin Layout.
Figure 9-11. 144-Pin LQFP Pin Layout
GPIO1, PCP_AD1 / D1
GPIO0, PCP_AD0 / D0
G
P
IO
25
, UA
RT
_
T
X
D
GP
IO
24,
U
A
R
T
_RX
D
GP
IO
31,
U
A
RT
_C
LK
XTO
VDD7
GND7
VDDIO7
XTI
GNDIO7
GNDA
NC
PLL_REF_RES
VDDA (3.3V)
VDD8
GND8
GPIO13, DAI1_DATA2, TM2, DSD2
GPIO14, DAI1_DATA3, TM3, DSD3
DAI1_DATA0, TM0, DSD0
GPIO12, DAI1_DATA1, TM1, DSD1
113
116
119
122
126
129
130
133
136
139
GPIO2, PCP_AD2 / D2
GPIO3, PCP_AD3 / D3
GPIO4, PCP_AD4 / D4
GPIO5, PCP_AD5 / D5
GPIO6, PCP_AD6 / D6
GP
IO
39,
P
C
P
_
C
S
,
S
C
P
2
_CS
GPIO7, PCP_AD7 / D7
GPIO9, PCP_A1 / A9
G
P
IO
3
8
,
PC
P_
W
R
/
D
S
,
SC
P2
_
C
L
K
VD
D
6
G
P
IO
4
0
,
PC
P_
R
D
/
R
W
GN
D
6
G
P
IO
1
0
,
PC
P_
A2
/
A1
0
,
SC
P2
_
M
O
S
I
G
P
IO
4
1
, PC
P_
IR
Q
, SC
P2
_
IR
Q
G
P
IO
3
7
, SC
P1
_
BSY,
PC
P
_
B
S
Y
VD
D
IO
6
G
P
IO
1
1
, PC
P_
A3
, AS,
SC
P2
_
M
IS
O
/ SD
A
GN
D
IO6
GP
OI
36,
S
C
P
1
_I
R
Q
G
P
IO
3
4
,
SC
P1
_
_
MI
SO
/
S
D
A
G
P
IO
3
3
, SC
P1
_
M
O
S
I
GP
IO
35,
S
C
P
1
_C
LK
VD
D
5
VD
D
IO
5
GN
D
5
GN
D
IO5
SD
_
C
A
S
SD
_
R
A
S
SD_A3, EXT_A3
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
10
1
98 94 91 86 83 76 73
S
D
_A
10,
E
X
T
_
A
1
0
SD_A11, EXT_A11
VDD4
GND4
SD
_
C
S
SD_A4, EXT_A4
SD_A5, EXT_A5
SD_A6, EXT_A6
SD_A7, EXT_A7
SD_A8, EXT_A8
SD_CLKEN
SD_A9, EXT_A9
VDDIO4
GNDIO4
SD_CLKOUT
SD_CLKIN
SD_D10, EXT_D10
SD_D11, EXT_D11
SD_D12, EXT_D12
VDD3
GND3
SD_D13, EXT_D13
SD_D14, EXT_D14
SD_D15, EXT_D15
SD_DQM1
S
D
_D
7,
E
X
T
_D7
S
D
_D
6,
E
X
T
_D6
VDDIO3
GNDIO3
S
D
_D
5,
E
X
T
_D5
SD
_
D
Q
M
0
S
D
_D
4,
E
X
T
_D4
S
D
_D
3,
E
X
T
_D3
S
D
_D
2,
E
X
T
_D2
69
66
63
60
57
54
47
44
1
GPIO26
G
P
IO
1
7
, D
A
O
1
_
D
A
T
A3
/
XM
T
A
GP
IO
15,
DA
O1_D
A
T
A
1
,
H
S
1
DA
O1_D
A
T
A
0
, H
S
0
DA
O
1
_
L
RC
LK
DAI1_LRCLK, DSD5
DA
O
_
M
C
LK
G
P
IO
2
0
, D
A
O
2
_
D
AT
A2
, EE_
C
S
DAI1_SCLK, DSD_CLK
VD
D
1
G
ND1
DA
O
1
_
S
C
L
K
GP
IO
16,
DA
O1_D
A
T
A
2
,
H
S
2
GP
IO
2
3
, D
A
O2
_LR
C
L
K
RE
S
E
T
V
DDI
O
1
GP
IO
22,
D
A
O2
_S
C
L
K
G
NDI
O
1
GP
IO
18
, DA
O2_D
A
T
A
0
,
H
S
3
GP
IO
19
, DA
O2_D
A
T
A
1
,
H
S
4
V
DD2
G
ND2
AT
A
3
/
XM
T
B
, U
A
R
T
_
T
X_
EN
A
B
L
E
V
DDI
O
2
GN
D
IO2
SD
_
W
E
SD_D0, EXT_D0
SD_D1, EXT_D1
5 9 10 13 18 21 24 27 33 36
SD_D8, EXT_D8
SD_D9, EXT_D9
SD_A12, EXT_A12
SD
_
B
A1
, E
X
T
_
A
1
4
S
D
_
BA0
, EX
T
_
A1
3
G
P
IO
3
2
, SC
P1
_
C
S
,
IO
W
A
IT
VDDIO8
GNDIO8
EXT
_
A
1
5
EXT
_
A
1
6
EXT
_
A
1
7
EXT
_
A
1
8
EXT
_
A
1
9
EXT
_
C
S1
GPIO8, PCP_A0 / A8
EXT_CS2
EXT
_
O
E
EXT_WE GPIO27
G
P
IO
2
8
, D
D
A
C
GP
IO
29,
X
M
T
A
_I
N
GP
IO
30,
X
M
TB
_I
N
T
EST
DB
DA
DB
CK
XTAL_OUT
GPIO43, BDI_CLK, DAI2_SCLK
GPIO42, BDI_REQ , DAI2_LRCLK, PCP_IRQ / BSY
DAI1_DATA4, BDI_DATA, DAI2_DATA, DSD4
CS4953xx
144 LQFP
15 25 30 35
37
40
45
50
55
65
70
72
75 80 85 90 95 10
0
10
5
108
109
110
115
120
125
135
140
144