Cirrus Logic CS4953xx - Manual (Page 13)

1-5 Copyright 2010 Cirrus Logic, Inc. DS732UM10
Functional Overview of the CS4953xx Chip
CS4953xx Hardware User’s Manual
By default, SCP2 is configured as a master to access a serial FLASH/EEPROM for either booting the
DSP or retrieving configuration information. As a master, it can drive the clock signal at up to 1/2 of the
DSP’s core clock speed.
The CS4953xx has two additional serial communication pins not specified in either the I
2
C or SPI
specification. The port uses the SCP1_IRQ pin to indicate that a read message is ready for the host. The
port uses the SCP1_BSY pin to warn the host to pause communication.
A serial control port can be operated simultaneously with the CS4953xx parallel control port.
1.2.11 SDRAM Controller
The CS4953xx supports a glueless external SDRAM interface to extend the data memory of the DSP
during runtime. The SDRAM controller provides 2-port access to X and Y memory space, a quad-word
read buffer, and a double-buffered quad-word write buffer. One SDRAM controller port is dedicated to P
memory space and the second port is shared by X and Y memories. The X/Y port has dual write buffers
and a single read buffer, and the P memory port has a single read buffer. One of these buffers is four 32-
bit words (128 bits). Every “miss” to the read buffer will cause the SDRAM controller to burst eight 16-bit
reads on the SDRAM interface. The SDRAM controller supports SDRAMs from 2 MB to 64 MB with
various row, bank, and column configurations. The SDRAM controller runs synchronous to HCLK, the
global chip clock.
1.2.12 Flash Controller
The CS4953xx supports a glueless external Flash interface that allows autoboot from a parallel Flash or
EEPROM device extending data memory and/or program memory during DSP runtime. Flash can be
accessed using 8-bit, 16-bit, and 32-bit data modes (1-byte, 2-byte, and 4-byte words) and using an 8-bit
or 16-bit data bus, where the word width is the number of bytes per transfer, and the data bus size is the
width of the physical interface to Flash. Separate chip select pins allow Flash devices to be connected
without additional chip select logic. Thus, the interface supports up to 512k x 16 bits of Flash. The external
Flash interface serially accesses the X, Y, and P memory spaces on the CS4953xx chip.
1.2.13 DMA Controller
The DMA controller contains 12 stereo channels. The O/S uses 11 stereo channels, 6 for the DAO (2 are
for the S/PDIF transmitters), 4 for the DAI, and one for the parallel control port. The addition of the DMA
channel for the parallel control port allows compressed audio data to be input over this port. The DMA
block is able to move data to/from X or Y memory, or alternate between both X and Y memory. The DMA
controller moves data to/from X and/or Y memory opportunistically (if the core is not currently accessing
that particular memory space during the current cycle). The DMA controller has a “Dead Man’s” timer so
that if the core is running an inner loop and accessing memory every cycle, the DMA controller can
interrupt the core to run a DMA cycle.
1.2.14 Timers
A 32-bit timer block runs off the CS4953xx DSP clock. The timer count decrements with each clock tick of
the DSP clock when the timer is enabled. When the timer count reaches zero, it is re-initialized, and may
be programmed to generate an interrupt to the DSP.