Cirrus Logic CS4953xx User Manual
Page 114
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-
GPIO4
General Purpose
Input/Output
1. PCP_D4
2. PCP_AD4
1. Parallel Control Port Data
Bus
2. Parallel Control Port
Multiplexed Address and Data
Bus
3.3V
(5V tol)
BiDir
IN
Y
116
9
GNDIO7
I/O ground
0V
PWR
117
-
GPIO3
General Purpose
Input/Output
1. PCP_D3
2. PCP_AD3
1. Parallel Control Port Data
Bus
2. Parallel Control Port
Multiplexed Address and Data
Bus
3.3V
(5V tol)
BiDir
IN
Y
-
10
GPIO3
General Purpose
Input/Output
3.3V
(5V tol)
BiDir
IN
Y
118
-
GPIO2
General Purpose
Input/Output
1. PCP_D2
2. PCP_AD2
1. Parallel Control Port Data
Bus
2. Parallel Control Port
Multiplexed Address and Data
Bus
3.3V
(5V tol)
BiDir
IN
Y
-
11
GPIO2
General Purpose
Input/Output
1. UART_TXD
1. UART Output
3.3V
(5V tol)
BiDir
IN
Y
119
12
VDD7
Core power supply
voltage
1.8V
PWR
120
-
GPIO1
General Purpose
Input/Output
1. PCP_D1
2. PCP_AD1
1. Parallel Control Port Data
Bus
2. Parallel Control Port
Multiplexed Address and Data
Bus
3.3V
(5V tol)
BiDir
IN
Y
13
GPIO1
General Purpose
Input/Output
1. UART_RXD
1. UART Input
3.3V
(5V tol)
BiDir
IN
Y
121
-
GPIO0
General Purpose
Input/Output
1. PCP_D0
2. PCP_AD0
1. Parallel Control Port Data
Bus
2. Parallel Control Port
Multiplexed Address and Data
Bus
3.3V
(5V tol)
BiDir
IN
Y
Table 9-10. Pin Assignments (Continued)
LQFP-
144
Pin #
LQFP-
128
Pin #
Function 1
(Default)
Description of Default
Function
Secondary Functions
Description of Secondary
Functions
Pwr
Type
Reset
State
Pullup
at
Reset