Cirrus Logic CS4953xx - Manual (Page 18)

Slave Boot Procedures
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 2-4
2.3 Slave Boot Procedures
When the CS4953xx is the slave boot device, the system host controller (as the master boot device) must
follow an outlined procedure for correctly loading application code. The two methods of slave boot for the
CS4953xx, slave boot and host-controlled master boot are described in this section. Each of these
methods requires the system host controller to send messages to, and read back messages from, the
CS4953xx. These messages have been outlined in
Section 2.3.3 "Boot Messages" on page 2-10 .
The CS4953xx has different .uld files (overlays) for certain processing tasks. Slave booting the CS4953xx
requires loading multiple overlays - differing from previous Cirrus Logic Audio DSP families (this is,
CS493xx, CS494xxx). Please refer to AN288, “CS4953xx Firmware User’s Manual” regarding more
information on the breakdown of processing tasks for each overlay.
Pseudocode and flowcharts will be used to describe each of these boot procedures in detail. The flow
charts use the following messages:
• Write_* – Write to CS4953xx
• Read_* – Read from CS4953xx
Please note that * above can be replaced by SPI, I 2 C, Intel ® , Multiplexed Intel, or Motorola ® depending on
the mode of host communication. For each case, the general download algorithm is the same. The
system designer should also refer to the control port sections of this document in
Chapter 3, "" , Chapter 3,
"Serial Control Port" and Chapter 4, "" , Chapter 4, "Parallel Control Port" for the details of when writing to
and reading from the CS4953xx is valid.
One feature that is of special note – the entire boot procedure for the CS4953xx can be made of a
combination of slave boot and host-controlled master boot procedures. An example can be seen in
Figure 2-3 on page 8 .
After completing the full download to the CS4953xx, a KICK START message is sent to cause the
application code begin execution. Please note that it takes time to lock the PLL and initialize the SDRAM
interface when initially booting the DSP. Typically this time is less than 200 ms. If a message is sent to the
DSP during this time, the SCP1_BSY pin will go low to indicate that the DSP is busy. Any messages sent
when the SCP1_BSY pin is LOW will be lost. If the SCP1_BSY pin stays LOW longer than 200 ms the
host must reboot the DSP.
2.3.1 Host Controlled Master Boot
The Host Controlled Master Boot (HCMB) procedure is a sequence where the system host controller
instructs the CS4953xx to boot application code from either the external memory interface (ROM or
Flash), or the serial control interface (serial SPI Flash/EEPROM or I
2
C EEPROM). The system host
controller can communicate with the CS4953xx via SPI, I
2
C, or one of the three parallel formats (Intel,
Multiplexed Intel, or Motorola). The external memory start address of the code image, as well as the data
rate, are specified by the host by the HCMB_<MODE> message. These messages are defined in
Section
2.3.3 "Boot Messages" on page 2-10 .