Cirrus Logic CS4953xx - Manual (Page 47)

3-15 Copyright 2010 Cirrus Logic, Inc. DS732UM10
SPI Port
CS4953xx Hardware User’s Manual
3.4.1 SPI System Bus Description
The SPI bus is a multi-master bus. This means that more than one device capable of controlling the bus
can be connected to it. Generation of clock signals on the SPI bus is always the responsibility of master
devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals
from a master cannot be altered by any other device on the bus, otherwise a collision will occur. The slave
chip-select signals can only be controlled by master devices.
The CS4953xx has two serial ports. However, the O/S currently supports only slave mode host
communication on SCP1, and master mode communication on SCP2 for booting from a serial EEPROM/
FLASH.
SCP1_MOSI (Master Out/Slave In) and SCP1_MISO (Master In/Slave Out) are bidirectional lines that
change their behavior depending on whether the device is operating in master or slave mode. Only the
master can drive the MOSI signal while only the slave can drive the MISO signal.
Figure 3-13. Block Diagram of SPI System Bus
As seen in Figure 3-12 , two serial ports are available on the CS4953xx. Each can be configured to either
a master or slave. For audio applications, SCP1 is configured as a slave port and SCP2 is configured as a
master port. SCP2 is used only in systems that are booting from serial EEPROM.
3.4.2 SPI Bus Dynamics
A SPI transaction begins by the master driving the slave chip select SCP1_CS low. SPI transactions end
by the master driving the SCP1_CS high. This SPI bus is considered busy while any device’s SCP1_CS
signal is low. The bus is free only when all slave SCP1_CS signals are high. A high-to-low transition on
the SCP1_CS line defines an SPI Start condition. A low-to-high transition on the SCP1_CS line defines an
SPI Stop condition. Start and Stop conditions are always generated by the master. The bus is considered
to be busy after the Start condition. The bus is considered to be free again following the Stop condition.
SCP2_IRQ
Serial Control Port Data Ready Interrupt Request Output, Active
Low
This pin is driven low when the DSP has a message for the host
to read. The pin will go high when the host has read the
message and the DSP has no further messages. This pin
reflects the state of the SCP1 port Transmit Buffer Empty Flag.
108 5
Open
Drain
Table 3-2. Serial Control Port SPI Signals (Continued)
Pin Name Pin Description
LQFP-144
Pin #
LQFP-128
Pin #
Pin Type
R E SE T
SC P 1_C S
SC P 1_C LK
SC P 1_M O SI
SC P 1_M ISO
SC P 1_IR Q
SC P 1_B S Y
S ystem
M icrocontroller
C S 4953xx
M O SI
M ISO
S P I E E P R O M
M O SI
M ISO
R E SE T
C S
C LK SC P 2_C LK
SC P 2_M O SI
SC P 2_M ISO
EE _C S
3.3k 3.3k
3.3V
MA
S
T
E
R
ON
L
Y
S
L
AV
E
ONLY