Cirrus Logic CS4953xx User Manual
Page 112
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104
-
GPIO39
General Purpose
Input/Output
1. PCP_CS
2. SCP2_CS
1. Parallel Port Chip Select
(Intel/Motorola/Multiplexed
Mode)
2. SPI Chip Select
3.3V
(5V tol)
BiDir
IN
Y
105
-
GPIO11
General Purpose
Input/Output
1. PCP_A3
2. PCP_AS
3. SCP2_MISO
4. SCP2_SDA
1. Parallel Control Port
Address Bit 3
2. Parallel Control Port
Address Strobe
3. SPI Mode Master Data
Input/Slave Data Output
4. I
2
C Mode Master/Slave
Data IO
3.3V
(5V tol)
BiDir/
OD
IN
Y
-
2
GPIO11
General Purpose
Input/Output
1. SCP2_MISO
2. SCP2_SDA
1. SPI Mode Master Data
Input/Slave Data Output
2. I
2
C Mode Master/Slave
Data IO
3.3V
(5V tol)
BiDir/
OD
IN
Y
106
-
GPIO10
General Purpose
Input/Output
1. PCP_A2
2. PCP_A10
3. SCP2_MOSI
1. Parallel Control Port
Address Bit 2
2. Parallel Control Port
Address Bit 10
3. SPI Mode Master Data
Output/Slave Data Input
3.3V
(5V tol)
BiDir
IN
Y
-
3
GPIO10
General Purpose
Input/Output
1. SCP2_MOSI
1. SPI Mode Master Data
Output/Slave Data Input
3.3V
(5V tol)
BiDir
IN
Y
107
-
GPIO40
General Purpose
Input/Output
1. PCP_RD
2. PCP_R/W
1. Parallel Read Select (Intel
Mode)
2. Parallel Read/Write Select
(Motorola and Multiplexed
Mode)
3.3V
(5V tol)
BiDir
IN
Y
108
-
GPIO41
General Purpose
Input/Output
1. PCP_IRQ
2. SCP2_IRQ
1. Parallel Control Port Data
Ready Interrupt Request
2. Serial Control Port Data
Ready Interrupt Request
3.3V
(5V tol)
BiDir/
OD
IN
Y
Table 9-10. Pin Assignments (Continued)
LQFP-
144
Pin #
LQFP-
128
Pin #
Function 1
(Default)
Description of Default
Function
Secondary Functions
Description of Secondary
Functions
Pwr
Type
Reset
State
Pullup
at
Reset