Cirrus Logic CS4953xx - Manual (Page 86)

SDRAM/Flash Controller Interface
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 8-8
DynamicRasCas0
Configure the active bank A to active bank B latency
Bit 31:10 = 0 = Reserved
Bit 9:8 = CAS latency (CAS),where:
00 = reserved
01 = one clock cycle
10 = two clock cycles
11 = three clock cycles
Bit 7:2 = 0 = Reserved, rCAS latency (CAS),where:
Bit 1:0 = RAS latency (RAS),where:
00 = reserved
01 = one clock cycle
10 = two clock cycles
11 = three clock cycles
0x8100006F
0xHHHHHHHH
Default 0x00000303
StaticConfig0 (Not Supported)
Bit 31:2 = 0 = Reserved
Bit 1:0 = Memory Bus Width, where:
00 = SRAM Memory bus 8 bits wide.
01 = SRAM Memory bus 16 bits wide.
10 = Reserved
11 = Reserved
0x81000070
0xHHHHHHHH
Default 0x00000000
StaticWaitWen0 (Not Supported)
EXT_CS falling to EXT_WE falling (t
xmcswe
)
Bit 31:4 = 0 = Reserved
Bit 3:0 =SRAM_WEN_CYCLE, where:
0000 = one DSP clk cycle between the assertion of chip select and write
enable. 0001 to 1111 = (n+1) cycle delay.
t
xmcswe
=(SRAM_WEN_CYCLE + 1 )*HCLK
0x81000071
0xHHHHHHHH
Default 0x00000000
StaticWaitOen0 (Not Supported)
EXT_CS falling to EXT_OE falling (t
xmcsoe
)
Bit 31:4 = 0 = Reserved
Bit 3:0 =SRAM_OEN_CYCLE, where:
0000 = no delay between the assertion of chip select and output enable.
0001 to 1111 = (n) cycle delay.
t
xmcsoe
=(SRAM_OEN_CYCLE )*HCLK
0x81000072
0xHHHHHHHH
Default 0x00000000
StaticWaitRd0 (Not Supported)
Single Word Read Cycle (t
xmrdc
)
Bit 31:5 = 0 = Reserved
Bit 4:0 =SRAM_RD_CYCLE, where:
00000 to 11110 = (n+1) HCLK cycle for Read Cycle.
t
xmrdc
=(SRAM_RD_CYCLE + 1 )*HCLK - 6.87ns
0x81000073
0xHHHHHHHH
Default 0x0000001F
StaticWaitWr0 (Not Supported)
EXT_CS falling to EXT_WE rising (t
xmcswa
)
Bit 31:5 = 0 = Reserved
Bit 4:0 =SRAM_WR_CYCLE, where:
00000 to 11110 = (n+2) HCLK cycle for Write access time.
t
xmcswa
=(SRAM_WR_CYCLE + 2)*HCLK
0x81000075
0xHHHHHHHH
Default 0x0000001F
Table 8-2. SDRAM/Flash Controller Parameters (Continued)
Mnemonic Hex Message