Cirrus Logic CS4953xx - Manual (Page 14)

Functional Overview of the CS4953xx Chip
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 1-6
1.2.15 Clock Manager and PLL
The CS4953xx Clock Manager and PLL module contains an Analog PLL, RTL Clock Synthesizer, and
Clock Manager. The Analog PLL is a customized analog hard macro that contains the Phase Detector
(PD), Charge Pump, Loop Filter, VCO, and other non-digital PLL logic. The Clock Synthesizer is a digital
design wrapper around the analog PLL that allows clock frequency ranges to be programmed. The Clock
Manager is a digital design wrapper for the Clock Synthesizer that provides the logic (control registers)
necessary to meet chip clocking requirements.
The Clock Manager and PLL module generates two master clocks:
• HCLK - global chip clock (clocks the DSP core, internal memories, SDRAM, Flash, and all
peripherals)
• OVFS - oversampled audio clock. This clock feeds the DAO block which has dividers to generate
the DAO_MCLK, DAO_SCLK, and DAO_LRCLK.
The Clock Manager has the ability to bypass the PLL so that the HCLK will run directly off the PLL
Reference Clock (REFCLK). While operating in this mode, the OVFS clock can still be divided off the VCO
so the PLL can be tested.
1.2.16 Programmable Interrupt Controller
The Programmable Interrupt Controller (PIC) forces all incoming interrupts to be synchronized to the
global clock, HCLK. The PIC provides up to 16 interrupts to the DSP Core. The interrupts are prioritized
with interrupt 0 as the highest priority and interrupt 15 as the lowest priority. Each interrupt has a
corresponding interrupt address that is also supplied to the DSP core. The interrupt address is the same
as the IRQ number (interrupt 0 uses interrupt address 0 and interrupt 15 uses interrupt address 15). Both
an enable mask and a run mask are provided for each interrupt. The enable mask allows the enabled
interrupts to generate a PIC_REQ signal to the DSP core, and the run mask allows the enabled interrupts
to generate a PIC_CLR, thereby bringing the core out of its halt state when it accepts the interrupt.
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