Cirrus Logic CS4953xx - Manual (Page 51)

3-19 Copyright 2010 Cirrus Logic, Inc. DS732UM10
SPI Port
CS4953xx Hardware User’s Manual
3.4.3.4 SPI Read Protocol
1. An SPI read transaction is initiated by the CS4953xx slave driving SCP1_IRQ low to indicate that it
has data to be read.
2. The master begins a SPI transaction driving chip select (SCP1_CS) low.
3. This is followed by a 7-bit address and the read/write bit set high for a read. So, the master should
send 0x81. The 0x81 byte represents the 7-bit SPI address 1000000b, and the least significant bit set
to ‘1’, designates a read.
4. After the falling edge of the serial control clock (SCP1_CLK) for the read/write bit, the master can
begin clocking out the 4-byte word from the CS4953xx on the MISO pin. Data clocked out of the
CS4953xx by the master is valid on the rising edge of SCP1_CLK and data transitions occur on the
falling edge of SCP1_CLK. The serial clock should be held low so that eight transitions from low-to-
high-to-low will occur for each byte.
5. If SCP1_IRQ is still low after 4 bytes, then proceed to Step 4 and read another 4 bytes out of the
CS4953xx slave.
6. If SCP1_IRQ is high, the SCP1_CS line of CS4953xx should be driven high to end the read
transaction.