Cirrus Logic CS4953xx - Manual (Page 53)

3-21 Copyright 2010 Cirrus Logic, Inc. DS732UM10
SPI Port
CS4953xx Hardware User’s Manual
3.4.3.5 SCP1_IRQ Behavior
The SCP1_IRQ signal is not part of the SPI protocol, but is provided so that the slave can signal that it has
data to be read. A high-to-low transition on SCP1_IRQ indicates to the master that the slave has data to
be read. When a master detects a high-to-low transition on SCP1_IRQ, it should send a Start condition
and begin reading data from the slave.
SCP1_IRQ is guaranteed to remain low (once it has gone low), until the rising edge of SCP1_CLK for the
last bit of the last byte to be transferred out of CS4953xx. If there is no more data to be transferred,
SCP1_IRQ will go high at this point. After going high, SCP1_IRQ is guaranteed to stay high until the rising
edge of SCP1_CS.
This end-of-transfer condition signals the master to end the read transaction by clocking the last data bit
out of CS4953xx and then driving the CS4953xx SCP1_CS line high to signal that the read sequence is
over. If SCP1_IRQ is still low after the rising edge of SCP1_CLK on the last data bit of the current byte,
the master should continue reading data from the serial control port. It should be noted that all data should
be read out of the serial control port during one cycle or a loss of data will occur. In other words, all data
should be read out of the chip until SCP1_IRQ signals the last byte by going high as described above.
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