Cirrus Logic CS5376A - Manual (Page 44)

CS5376A
DS612F4 44
SINC1 – Single stage, fixed decimate by 8
5 th order decimate by 8, 36 coefficients
SINC2 – Multi-stage, variable decimation
Stage 1: 4 th order decimate by 2, 5 coefficients
Stage 2: 4 th order decimate by 2, 5 coefficients
Stage 3: 5 th order decimate by 2, 6 coefficients
Stage 4: 6 th order decimate by 2, 7 coefficients
SINC3 – Multi-stage, variable decimation
Stage 1: 4
th
order decimate by 5, 17 coefficients
Stage 2: 4 th order decimate by 5, 17 coefficients
Stage 3: 4 th order decimate by 5, 17 coefficients
Stage 4: 5 th order decimate by 2, 6 coefficients
Stage 5: 6 th order decimate by 2, 7 coefficients
Stage 6: 6 th order decimate by 3, 13 coefficients
Figure 24. SINC Filter Stages
SINC filters
FIR2
Output
Word
Rate DEC Bit
Setting SINC1
Deci-
mation SINC2
Deci-
mation SINC2
Stages SINC3
Deci-
mation SINC3
Stages
4000 0111 8 2 4 - -
2000 0110 8 4 3,4 - -
1000 0101 8 8 2,3,4 - -
500 0100 8 16 1,2,3,4 - -
333 0011 8 8 2,3,4 3 6
250 0010 8 16 1,2,3,4 2 5
200 0001 8 2 4 20 3,4,5
125 0000 8 16 1,2,3,4 4 4,5
100 1111 8 4 3,4 20 3,4,5
50 1110 8 8 2,3,4 20 3,4,5
40 1101 8 2 4 100 2,3,4,5
25 1100 8 16 1,2,3,4 20 3,4,5
20 1011 8 4 3,4 100 2,3,4,5
10 1010 8 8 2,3,4 100 2,3,4,5
5 1001 8 16 1,2,3,4 100 2,3,4,5
1 1000 8 16 1,2,3,4 500 1,2,3,4,5
Table 9. SINC Filter Configurations