Cirrus Logic CS5376A - Manual (Page 71)

CS5376A
DS612F4 71
20.3.1 SPI 2 Control Register
The SPI 2 hardware is configured by the
SPI2CTRL digital filter register (0x10).
Bits in this register select the serial input pin and
chip select pin used for a transaction, set the total
number of bytes in a transaction, initiate a serial
transaction, and report status information about a
transaction. Other bits in SPI2CTRL set hardware
configuration options such as the serial clock rate,
the SPI mode, and the state of internal pull-up re-
sistors.
Chip Select Enable - CS[4:0]
The chip select pin to use during a transaction is se-
lected by the CS0, CS1, CS2, CS3, and CS4 bits.
Multiple chip selects can be enabled to send a
transaction to more than one serial peripheral.
Serial Input Select - SPI2EN[4:1], RCH[1:0]
Which serial input pin will receive data is selected
using the SPI2EN bits and the RCH bits. The
SPI2EN bits enable the serial input, while the RCH
bits select it for the SPI 2 transaction.
A channel’s SPI2EN bit should always be enabled,
even when transactions do not expect to receive
data from the slave device.
Transaction Bytes - DNUM[2:0]
DNUM bits specify the total number of bytes to
transfer during a serial transaction, including com-
mand and address bytes. DNUM is zero based and
represents one greater than the number pro-
grammed.
Serial Clock Rate - SCKFS[2:0]
The serial clock rate output from the SCK2 pin is
selected by the SCKFS bits. Serial clock rates
range from 32 kHz to 4.096 MHz.
SPI Mode - SCKPO, SCKPH
The serial mode used for a transaction depends on
the SCKPO and SCKPH bits. The SPI 2 port sup-
ports all four SPI modes, with mode 0 and mode 3
the most commonly used. Supported modes are:
SPI Mode 0 (0,0): SCKPO = 0, SCKPH = 0
SPI Mode 1 (0,1): SCKPO = 0, SCKPH = 1
SPI Mode 2 (1,0): SCKPO = 1, SCKPH = 0
SPI Mode 3 (1,1): SCKPO = 1, SCKPH = 1
Wired-Or Mode - WOM
The SPI 2 pins can operate in two modes depend-
ing on the WOM bit. A default push-pull configu-
ration drives output signals both high and low.
Wired-Or mode only drives low, relying on a weak
internal pull-up resistor to pull the output high.
Wired-Or mode permits multiple serial controllers
to access the same bus without contention.
Initiating Serial Transactions - D2SREQ
Writing the D2SREQ bit starts an SPI 2 serial
transaction. When complete, the D2SREQ bit is au-
tomatically cleared by the SPI 2 hardware.
Status and Error Bits - D2SOP, SWEF, TM
Three bits in the SPI2CTRL register report status
and error information.
D2SOP is set when the SPI 2 port is busy perform-
ing a transaction. It is automatically cleared when
the transaction is completed.
SWEF is set if a request to initiate a new transac-
tion occurs during the current transaction. This flag
is latched and must be cleared manually.
TM is set to indicate the SPI 2 port timed out on the
requested transaction. This flag is latched and must
be cleared manually.
20.3.2 SPI 2 Command Register
The SPI2CMD register (0x11) is a 16-bit digital fil-
ter register with the high byte designated as an SPI
command and the low byte designated as an ad-
dress. The high byte holds an 8-bit SPI ‘write’ or
‘read’ opcode, as shown in Figure 38, and the low
byte holds an 8-bit serial address.