Cirrus Logic CS5376A - Manual (Page 62)

CS5376A
62 DS612F4
BRK digital filter register (0x29) programs the
sample delay for the TB bit output. See “Time
Break Controller” on page 67 for more information
about time break.
FIFO Overflow Bit - W
The FIFO overflow bit indicates an error condition
in the SD port data FIFO, and is set if new digital
filter data overwrites a FIFO location containing
data which has not yet been sent.
The W bit is sticky, meaning it persists indefinitely
once set. Clearing the W bit requires sending the
‘Filter Stop’ and ‘Filter Start’ configuration com-
mands to reinitialize the data FIFO.
Conversion Data Word
The lower 24-bits of the SD port output data word
is the conversion sample for the specified channel.
Conversion data is 24-bit two’s complement for-
mat.
16.3 SD Port Transactions
The SD port can operate in two modes depending
how the SDTKI pin is connected: request mode
where data is output when requested by the com-
munications channel, or continuous mode where
data is output immediately when ready.
16.3.1 Request Mode
To initiate SD port transactions on request, SDTKI
is connected to an active high polling signal from
the communications channel. A rising edge into
SDTKI when new data is available in the SD port
FIFO causes the CS5376A to initiate an SD port
transaction by driving SDRDY low. If data is not
yet available in the SD port FIFO, the SDTKI sig-
nal is passed through to the SDTKO output.
Once an SD port transaction is initiated, serial
clocks into SDCLK cause data to be output to
SDDAT, as shown in Figure 33. When all available
Data Status
0 23 31
-- MFLAG CH[1] CH[0] W
31 29 30 28 27 26 25 24
Figure 32. SD Port Data Format
TB --
Word 1 Word 4 Word 2 Word 3
Status Data
128 bits
--
00 - Channel 1
01 - Channel 2
10 - Channel 3
11 - Channel 4 0 - Modulator Ok
1 - Modulator Error
0 - No Time Break
1 - Time Break 0 - FIFO Ok
1 - FIFO Overflow