Figure 53. offset correction register offset1, Cs5376a, Bit definitions – Cirrus Logic CS5376A User Manual

Page 95

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CS5376A

DS612F4

95

23.2.9

OFFSET1 - OFFSET4 : 0x25 - 0x28

(MSB) 23

22

21

20

19

18

17

16

OFST23

OFST22

OFST21

OFST20

OFST19

OFST18

OFST17

OFST16

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

15

14

13

12

11

10

9

8

OFST15

OFST14

OFST13

OFST12

OFST11

OFST10

OFST9

OFST8

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

(LSB) 0

OFST7

OFST6

OFST5

OFST4

OFST3

OFST2

OFST1

OFST0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

DF Address: 0x25

--

Not defined;
read as 0

R

Readable

W

Writable

R/W

Readable and
Writable

Bits in bottom rows
are reset condition

Figure 53. Offset Correction Register OFFSET1

Bit definitions:

23:16 OFST[23:16]

Offset Correction
Upper Byte

15:8

OFST[15:8]

Offset Correction
Middle Byte

15:8

OFST[7:0]

Offset Correction
Lower Byte

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