Figure 46. gpio configuration register gpcfg0, Cs5376a, 2 gpcfg0 : 0x0e – Cirrus Logic CS5376A User Manual

Page 88

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background image

CS5376A

88

DS612F4

23.2.2

GPCFG0 : 0x0E

(MSB) 23

22

21

20

19

18

17

16

GP_DIR7

GP_DIR6

GP_DIR5

GP_DIR4

GP_DIR3

GP_DIR2

GP_DIR1

GP_DIR0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

15

14

13

12

11

10

9

8

GP_PULL7

GP_PULL6

GP_PULL5

GP_PULL4

GP_PULL3

GP_PULL2

GP_PULL1

GP_PULL0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

1

1

1

1

1

1

1

1

7

6

5

4

3

2

1

(LSB) 0

GP_DATA7

GP_DATA6

GP_DATA5

GP_DATA4

GP_DATA3

GP_DATA2

GP_DATA1

GP_DATA0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

1

1

1

1

1

1

1

1

DF Address: 0x0E

--

Not defined;
read as 0

R

Readable

W

Writable

R/W

Readable and
Writable

Bits in bottom rows
are reset condition

Bit

definitions:

Note: GPIO[4:0] also used as SPI 2 chip selects CS[4:0].

23:16 GP_DIR

[7:0]

GPIO pin direction
1: Output
0: Input

15:8

GP_PULL
[7:0]

GPIO pullup resistor
1: Enabled
0: Disabled

7:0

GP_DATA
[7:0]

GPIO data value
1: VDD
0: GND

Figure 46. GPIO Configuration Register GPCFG0

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