Figure 3. spi mode timing, Figure 3.spi mode timing – Cirrus Logic CS8420 User Manual
Page 10
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DS245F4
CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE
Inputs: Logic 0 = 0 V, Logic 1 = VD+; C
L
= 20 pF.
13. If Fso or Fsi is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fso and
less than 128 Fsi. This is dictated by the timing requirements necessary to access the Channel Status and
User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The
minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz
should be safe for all possible conditions.
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For f
sck
< 1 MHz.
Parameter
Symbol Min Typ
Max
Units
CCLK Clock Frequency
f
sck
0
-
6.0
MHz
CS High Time Between Transmissions
t
csh
1.0
-
-
μs
CS Falling to CCLK Edge
t
css
20
-
-
ns
CCLK Low Time
t
scl
66
-
-
ns
CCLK High Time
t
sch
66
-
-
ns
CDIN to CCLK Rising Setup Time
t
dsu
40
-
-
ns
CCLK Rising to DATA Hold Time
t
dh
18
-
-
ns
CCLK Falling to CDOUT Stable
t
pd
-
-
45
ns
Rise Time of CDOUT
t
r1
-
-
25
ns
Fall Time of CDOUT
t
f1
-
-
25
ns
Rise Time of CCLK and CDIN
t
r2
-
-
100
ns
Fall Time of CCLK and CDIN
t
f2
-
-
100
ns
t r2
t f2
t dsu
t dh
t sch
t scl
CS
CCLK
CDIN
t css
t pd
CDOUT
t csh
Figure 3. SPI Mode Timing