Cirrus Logic CS8420 - Manual (Page 22)

22 DS245F4
CS8420
7. AES3 TRANSMITTER AND RECEIVER
The CS8420 includes an AES3-type digital audio receiver and an AES3-type digital audio transmitter. A compre-
hensive buffering scheme provides read/write access to the channel status and user data. This buffering scheme is
described in
“Channel Status and User Data Buffer Management” on page 81 .
7.1 AES3 Receiver
The AES3 receiver accepts and decodes audio and digital data according to the AES3, IEC60958 (S/PDIF),
and EIAJ CP-1201 interface standards. The receiver consists of a differential input stage, accessed via pins
RXP and RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the
channel status and user data.
External components are used to terminate and isolate the incoming data cables from the CS8420. These
components are detailed in
“External AES3/SPDIF/IEC60958 Transmitter and Receiver Components” on
page 78 .
7.1.1 PLL, Jitter Attenuation, and Varispeed
Please see “PLL Filter” on page 87 for general description of the PLL, selection of recommended PLL filter
components, and layout considerations. Figure 5 shows the recommended configuration of the two ca-
pacitors and one resistor that comprise the PLL filter.
7.1.2 OMCK Out On RMCK
A special mode is available that allows the clock that is being input through the OMCK pin to be output
through the RMCK pin. This feature is controlled by the SWCLK bit in register 4 of the control registers.
When the PLL loses lock, the frequency of the VCO drops to 300 kHz. The SWCLK function allows the
clock from RMCK to be used as a clock in the system without any disruption when input is removed from
the Receiver.
7.1.3 Error Reporting and Hold Function
While decoding the incoming AES3 data stream, the CS8420 can identify several kinds of error, indicated
in the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked to the incoming AES3
data. The V bit reflects the current validity bit status. The CONF (confidence) bit indicates the amplitude
of the eye pattern opening, indicating a link that is close to generating errors. The BIP (bi-phase) error bit
indicates an error in incoming bi-phase coding. The PAR (parity) bit indicates a received parity error.
The error bits are “sticky” - they are set on the first occurrence of the associated error and will remain set
until the user reads the register via the control port. This enables the register to log all unmasked errors
that occurred since the last time the register was read.
The Receiver Error Mask register allows masking of individual errors. The bits in this register serve as
masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is con-
sidered unmasked, meaning that its occurrence will be reported in the receiver error register, will affect
the RERR pin, will invoke the occurrence of a RERR interrupt, and will affect the current audio sample
according to the status of the HOLD bits. The HOLD bits allow a choice of holding the previous sample,
replacing the current sample with zero (mute), or do not change the current audio sample. If a mask bit is
set to 0, the error is considered masked, meaning that its occurrence will not be reported in the receiver
error register, will not induce a pulse on RERR or generate a RERR interrupt, and will not affect the current
audio sample. The QCRC and CCRC errors do not affect the current audio sample, even if unmasked.