Cirrus Logic CS8420 - Manual (Page 89)

DS245F4 89
CS8420
16.3.2 Locking to the RXP/RXN Receiver Inputs
CS8420 parts that are configured to lock to only the RXP/RXN receiver inputs should use the external
PLL component values listed in
Table 18 and Table 19 . Values listed for the 32 to 96 kHz Fs range will
have the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the best
output jitter performance.
Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz
Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz*
* Parts used in applications that are required to pass the AES3 or IEC60958-4 specification for receiver
jitter tolerance should use these component values. Please note that the AES3 and IEC60958 specifica-
tions do not have allowances for locking to sample rates less than 32 kHz or for locking to the ILRCK input.
Also note that many factors can affect jitter performance in a system. Please follow the circuit and layout
recommendations outlined previously.
16.3.3 Locking to the ILRCK Input
CS8420 parts that are configured to lock to the ILRCK input should use the external PLL component val-
ues listed in
Table 20 . Note that parts that need to lock to both ILRCK and RXP/RXN should use
these values. Values listed for the 32 to 96 kHz Fs range will have the highest corner frequency jitter at-
tenuation curve, take the shortest time to lock, and offer the best output jitter performance.
Table 20. Locking to the ILRCK Input
Revision R
FILT
(k
Ω)
C
FILT
(
μF)
C
RIP
(nF) PLL Lock Time (ms)
D 0.909 1.8 33 56
D1 0.4 0.47 47 60
Revision R
FILT
(k Ω) C
FILT
( μF) C
RIP
(nF) PLL Lock Time (ms)
D 3.0 0.047 2.2 35
D1 1.6 0.33 4.7 35
Revision
Fs Range
(kHz) R
FILT
(k
Ω) C
FILT
(
μF) C
RIP
(nF) PLL Lock Time (ms)
D 8 to 96 1.3 2.7 62 120
D 32-96 5.1 0.15 3.9 70
D1 8 to 96 0.3 1.0 100 120
D1 32-96 0.6 0.22 22 70