Cirrus Logic CS8420 - Manual (Page 56)

56 DS245F4
CS8420
13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input)
Hardware Mode 1 data flow is shown in Figure 24 . Audio data is input via the AES3 receiver, and rate con-
verted. The audio data at the new rate is then output both via the serial audio output port and via the AES3
transmitter.
The channel status data, user data and validity bit information are handled in four alternative modes: 1A and
1B, determined by a start-up resistor on the COPY pin. In mode 1A, the received PRO, COPY, ORIG, EM-
PH, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied from
the received channel status data, and the transmitted U and V bits are 0.
In mode 1B, only the COPY and ORIG pins are output, and reflect the received channel status data. The
transmitted channel status bits, user data and validity bits are input serially via the PRO/C, EMPH/U and
AUDIO/V pins.
Figure 20 shows the timing requirements.
Start-up options are shown in Table 8 , and allow choice of the serial audio output port as a master or slave,
choice of four serial audio output port formats, and the source for transmitted C, U and V data. The following
pages contain the detailed pin descriptions for Hardware mode 1.
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held.
SDOUT RMCK RERR COPY Function
LO - - - Serial Output Port is Slave
HI - - - Serial Output Port is Master
- - - LO Mode1A: C transmitted data is copied from received data, U & V = 0,
received PRO, EMPH, AUDIO are visible.
- - - HI Mode 1B: CUV transmitted data is input serially on pins, received PRO,
EMPH, AUDIO are not visible
- LO LO Serial Output Format OF1
- LO HI Serial Output Format OF2
- HI LO Serial Output Format OF3
- HI HI Serial Output Format OF4
Table 8. Hardware Mode 1 Start-Up Options
AES3
Encoder
& Tx
Serial
Audio
Output
AES3 Rx
&
Decoder Sample
Rate
Converter
C & U bit Data Buffer
Clocked by
Output Clock Clocked by
Input Derived Clock
RXP
RXN
OLRCK
OSCLK
SDOUT
TXP
TXN
RMCK RERR COPY ORIG EMPH/U
TCBLD
PRO/C AUDIO/V TCBL MUTE
DFC0 DFC1 S/AES
VD+
H/S
Output
Clock
Source
OMCK
Power supply pins (VD+, VA+, DGND, AGND), the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 24. Hardware Mode 1 - Default Data Flow, AES3 Input